Missing PCH PCIe power and clock gating options in RPL-S Client FSP

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技术栈
c
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embedded-iot

调研方向

Start by comparing the RPL-S Client FSP configuration with the ADL-N IoT MR6 change referenced in the issue (commit 0a9eafc9737b1bca5224b4f5ff48b004b6f0d8f1). Check how the requested options are exposed and when the relevant registers are locked. Done means the RPL-S Client FSP exposes both options so board designs can disable PCIe power and clock gating.

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描述

Certain board designs don't route CLKREQ# from the PCIe slots to the PCH, and many add-in cards (for example datacenter GPUs) don't drive CLKREQ# at all. Such ports have to run with free-running reference clocks and no CLKREQ#. In that case PchPcieClockGating and PchPciePowerGating must be disabled, to avoid the issue described in https://review.coreboot.org/c/coreboot/+/76687.

The RPL-S Client FSP (RaptorLakeFspBinPkg/Client/RaptorLakeS, 12.0.200.80 / C.0.C8.50, the latest release) doesn't expose these options. It always enables PCH PCIe PHY power gating and clock gating, then locks the registers before FspSiliconInit returns. FspMultiPhaseSiInit reports zero phases on this platform, so there's no window for the bootloader to change them.

Could Intel please add PchPciePowerGating and PchPcieClockGating to the RPL-S Client FSP, as was done for ADL-N IoT in MR6 (#112, commit 0a9eafc9737b1bca5224b4f5ff48b004b6f0d8f1)?

Thanks

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