Open
Bluesim's symbol-probing interface has wrong values for FIFO
bluesimbuggood first issue
0 comments0 reactions0 assignees
Issues
Open
Properly support "enabled_when_ready" attribute for methods
enhancementgood first issue
0 comments0 reactions0 assignees
Open
Bluesim VCD for mkLFIFO has wrong FULL_N value
bluesimbuggood first issue
4 comments0 reactions0 assignees
Open
bsc crash when bs method arg name annotation doesn't match method arity
ICEerror-messagesgood first issue
4 comments0 reactions0 assignees
Open
better parse errors when missing endif preprocessor directive
error-messagesgood first issuesv-preprocessor
0 comments0 reactions0 assignees
Open
Better error message for -> instead of => in type signature
good first issue
3 comments0 reactions0 assignees
Open
SV preprocessor mis-interprets directives at end of file
buggood first issue
0 comments0 reactions0 assignees
Open
Output clocks of synthesized modules should be allowed to have no GATE port
enhancementgood first issuepre-github
2 comments0 reactions0 assignees
Open
Generate appropriate empty argument lists for Verilog system tasks/functions
good first issuepre-github
0 comments0 reactions0 assignees
Open
Syntax for enum encodings in BH/Classic
good first issue
0 comments0 reactions0 assignees
Open
1 comment0 reactions0 assignees
Open
Suggest missing 'valueOf' in error message
error-messagesgood first issue
0 comments0 reactions0 assignees
Open
Replace TmpNam.hs with temporary package
enhancementgood first issue
0 comments0 reactions0 assignees
Open
0 comments0 reactions0 assignees
Open
bsc accepts, ignores -o option with -verilog
enhancementgood first issue
2 comments0 reactions0 assignees
Open
update-build-version.sh: Allow setting git rev, instead of just NOGIT=1
buildgood first issue
1 comment0 reactions0 assignees