B-Lang-org/bsc

bsc does not update generated verilog/sim when BSV preprocessor macros changed

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#290 opened on Jan 8, 2021

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good first issue

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Description

package A;

module mkA();
`ifdef MY_MACRO
// behavior 1
rule behavior_1;
$display("behavior 1");
endrule
`else
// behavior 2
rule behavior_2;
$display("behavior 2");
endrule
`endif
endmodule
endpackage

If I first run

bsc -verilog -g mkA -D MY_MACRO  A.bsv

the generated verilog is based on the code in "behavior 1" block. But then, if I subsequently run:

bsc -u -verilog -g mkA A.bsv

The module is not recompiled and the Verilog is still based on "behavior 1" block. I expect bsc to analyze the module again and re-generate the verilog based on "behavior 2".

I need to manually remove the .bo files and rerun bsc to get the expected behavior.

Contributor guide

Research direction
Investigate how bsc tracks dependencies of preprocessor macros and why changes are not detected. Then propose a fix to include macro definitions in the dependency analysis.
Tech stack
haskell
Domain
build system
Issue type
Bug
DifficultyEstimated implementation difficulty for a new contributor, from 1 for very small changes to 5 for expert-level work.
2
Estimated timeA rough time range for an experienced contributor to investigate, implement, test, and prepare a pull request.
1-3 hours
Activity statusHow available the issue appears right now: fresh, active, stale, blocked, or waiting on maintainer input.
Active
ClarityHow clearly the issue explains the expected change, acceptance criteria, and next step.
Clear
Prerequisites
Git
Newbie friendlinessA 1-100 score estimating how approachable this issue is for first-time contributors.
75