B-Lang-org/bsc

Generate appropriate empty argument lists for Verilog system tasks/functions

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#304 opened on Feb 3, 2021

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good first issuepre-github

Description

When system tasks appear in the generated Verilog, this code in Verilog.hs omits the parenthesis when there are no arguments:

-- no parens when calling a task if it has no arguments                                                                                   
pPrint d p (VTask task []) = pPrint d 0 task <> text ";"

This was probably added because that is how the Verilog standard says that $finish should be written. However, for $fflush, the standard says that it must have empty parentheses, and some tools will be sticklers and issue a warning if the parentheses are missing.

The pPrint code will probably need to check the task name, to handle each specifically.

This is bug 1925 in Bluespec Inc's pre-GitHub bug database.

Contributor guide

Tech stack
None
Domain
backend
Issue type
bug
DifficultyEstimated implementation difficulty for a new contributor, from 1 for very small changes to 5 for expert-level work.
3
Estimated timeA rough time range for an experienced contributor to investigate, implement, test, and prepare a pull request.
1-3 hours
Activity statusHow available the issue appears right now: fresh, active, stale, blocked, or waiting on maintainer input.
stale
ClarityHow clearly the issue explains the expected change, acceptance criteria, and next step.
clear
Prerequisites
Basic HaskellVerilog system tasks
Newbie friendlinessA 1-100 score estimating how approachable this issue is for first-time contributors.
60
Research direction
Examine the pPrint function in Verilog.hs around the line handling VTask with no arguments. Modify the pattern to check the task name: for system tasks like $fflush, output empty parentheses instead of omitting them. Consult the Verilog standard for which system tasks require parentheses. The change is localized to that single clause.