B-Lang-org/bsc

Generate appropriate empty argument lists for Verilog system tasks/functions

Open

#304 opened on Feb 3, 2021

View on GitHub
 (0 comments) (0 reactions) (0 assignees)Haskell (178 forks)batch import
good first issuepre-github

Repository metrics

Stars
 (1,108 stars)
PR merge metrics
 (Avg merge 17d 1h) (18 merged PRs in 30d)

Description

When system tasks appear in the generated Verilog, this code in Verilog.hs omits the parenthesis when there are no arguments:

-- no parens when calling a task if it has no arguments                                                                                   
pPrint d p (VTask task []) = pPrint d 0 task <> text ";"

This was probably added because that is how the Verilog standard says that $finish should be written. However, for $fflush, the standard says that it must have empty parentheses, and some tools will be sticklers and issue a warning if the parentheses are missing.

The pPrint code will probably need to check the task name, to handle each specifically.

This is bug 1925 in Bluespec Inc's pre-GitHub bug database.

Contributor guide

Research direction
Check the pPrint function in Verilog.hs and add a case for system tasks that require empty parentheses, like $fflush, while keeping the no parens for $finish.
Tech stack
haskell
Domain
compilers
Issue type
Bug
DifficultyEstimated implementation difficulty for a new contributor, from 1 for very small changes to 5 for expert-level work.
2
Estimated timeA rough time range for an experienced contributor to investigate, implement, test, and prepare a pull request.
Under 1 hour
Activity statusHow available the issue appears right now: fresh, active, stale, blocked, or waiting on maintainer input.
Active
ClarityHow clearly the issue explains the expected change, acceptance criteria, and next step.
Clear
Prerequisites
Haskell
Newbie friendlinessA 1-100 score estimating how approachable this issue is for first-time contributors.
60