How to compile it to verilog!
Nobody has claimed this yet.
Assessment
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Newbie friendliness
- 25/100
- Issue type
- Documentation
- Clarity
- Needs clarification
- Activity status
- Stale
- Tech stack
- scala
- Domain
- build-system
Research direction
Start with Makefile:9 and the reported sbt and Windows build steps to determine how the repository expects its submodule to be initialized. Document the supported commands and prerequisites for generating Verilog for FPGA implementation, including how to avoid the reported non-repository error.
Written by the indexing model from the issue text.
Description
Hi,
I have installed sbt on my windows machine, and when I run make it would generate these errors,
git submodule update --init berkeley-testfloat-3
fatal: not a git repository (or any of the parent directories): .git
make: *** [Makefile:9: berkeley-testfloat-3/.git] Error 128
So How should I Generate Verilog for implementation of FPGA?
- Dominant language
- Scala
- Stars
- 393
- Forks
- 110
- PR merge metrics
- No merged PRs in 30d
Getting set up
This project ships no dev container, Dockerfile or contributing guide, so setting up is up to you: start from its README, and see our first-contribution guide for the general steps.
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
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