Chisel 7 Bump Issue due to Default Layers
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Assessment
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Newbie friendliness
- 35/100
- Issue type
- Bug
- Clarity
- Mostly clear
- Activity status
- Stale
- Tech stack
- scala
- Domain
- build-system
Research direction
Start with hardfloat/tests/src/FMATester.scala at the ChiselStage invocation around line 61, then inspect how Verilator consumes the generated Verilog. Confirm the behavior introduced by Chisel 7 default layers and choose between specializing them away or using per-module output with an include directory. Done means the generated Verilog is valid and the Verilator invocation can resolve its includes.
Written by the indexing model from the issue text.
Description
FYI: if this project tries to bump to Chisel 7, which now includes default layers, there will be problems with how the FMATester.scala generates Verilog here: https://github.com/ucb-bar/berkeley-hardfloat/blob/26f00d00c3f3f57480065e02bfcfde3d3b41ec51/hardfloat/tests/src/FMATester.scala#L61
With default layers always being there, then doing this may create an invalid single-file Verilog file that has `include directives pointing at directories/files which don't exist.
This can either be fixed by changing the ChiselStage invocation to include -enable-layers arguments that specialize away the default layers or this invocation could be changed to use one-file-per-module output and changing the Verilator invocation to properly setup +incdir pointing at the output directory.
- Dominant language
- Scala
- Stars
- 393
- Forks
- 110
- PR merge metrics
- No merged PRs in 30d
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