ucb-bar/chipyardScala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
The batteries-included testing and formal verification library for Chisel-based RTL designs.
Base NVDLA Workload for FireMarshal
Fork of upstream onnxruntime focused on supporting risc-v accelerators