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verilog simulator

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#13 1 comment 0 reactions 0 assignees View on GitHub

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Assessment

Difficulty
4/5
Estimated time
3-5 days
Newbie friendliness
25/100
Issue type
Feature
Clarity
Mostly clear
Activity status
Stale

Research direction

Start by locating the repository's Verilog testing setup and the commands that invoke Synopsys VCS. Investigate whether Verilator can replace that invocation and identify any compatibility gaps. Done means the existing Verilog tests run successfully without commercial tools; no specific files or tests are named in the issue.

Written by the indexing model from the issue text.

Description

It would be good to make Verilog testing independent from commercial tools - Synopsys VCS. A potential solution would be to use verilator instead.

Dominant language
Scala
Stars
393
Forks
110
PR merge metrics
No merged PRs in 30d

Getting set up

This project ships no dev container, Dockerfile or contributing guide, so setting up is up to you: start from its README, and see our first-contribution guide for the general steps.

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

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