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[Feature] Support STM32F103C6 (32KB Flash, 10KB RAM) on stm32f103-blue-pill

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Bewertung

Schwierigkeit
4/5
Geschätzter Aufwand
3-5 Tage
Anfängerfreundlichkeit
20/100
Issue-Typ
Feature
Klarheit
Klar beschrieben
Aktivitätsstatus
Veraltet
Tech-Stack
c
Bereich
embedded-iot

Rechercherichtung

The issue names bsp/stm32/stm32f103-blue-pill, including board.h, link.lds, rtconfig.py, board/Kconfig, README.md, and README_zh.md. Start by reviewing PR #11850, which the issue says already implements and verifies the proposed solution. Check its changes and validation against the C6 memory and peripheral constraints; the work is done when C6 builds fit its memory limits while the default C8 remains compatible.

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Beschreibung

Arch: ARM/AArch64 BSP BSP: STM32 enhancement
Affected area

Board Support Package (BSP)

Hardware/BSP vendor

STM32

Architecture

ARM / AArch64

Describe problem solved by the proposed feature

Currently, bsp/stm32/stm32f103-blue-pill only supports the STM32F103C8 chip (64KB/128KB Flash, 20KB RAM).
However, many widely available Blue Pill development boards on the market come populated with the lower-cost, pin-compatible STM32F103C6T6 (32KB Flash, 10KB RAM).

Attempting to run the existing BSP on an STM32F103C6 board causes several issues:

  1. Flash Overflow: The default firmware image exceeds 32KB, failing to fit or link for the C6 flash boundary.
  2. RAM Corruption: board.h and the linker script assume 20KB SRAM (HEAP_END at 0x20005000), whereas C6 has only 10KB SRAM (HEAP_END at 0x20002800). Any heap allocation past 10KB causes silent memory corruption or HardFault.
  3. Peripheral Differences: STM32F103C6 silicon physically lacks USART3 and SPI2.
Describe your preferred solution

Add support for the STM32F103C6 variant to bsp/stm32/stm32f103-blue-pill while keeping 100% backward compatibility for the default STM32F103C8:

  1. Kconfig Chip Choice:

    • Add a choice between SOC_STM32F103C8 (default) and SOC_STM32F103C6.
    • When C6 is selected, automatically select RT_USING_SMALL_MEM, RT_USING_SMALL_MEM_AS_HEAP, and RT_KLIBC_USING_LIBC_VSSCANF.

  2. Accurate Memory Boundaries (board.h & link.lds):

    • Dynamically define STM32_FLASH_SIZE (32KB) and STM32_SRAM_SIZE (10KB) under SOC_STM32F103C6 so HEAP_END is strictly bounded at 0x20002800.
    • Update link.lds with dynamic _ROM_SIZE and _RAM_SIZE symbols.
    • Pass -Os and --defsym=_ROM_SIZE=32k,--defsym=_RAM_SIZE=10k in rtconfig.py for C6 builds.

  3. Peripheral Constraints (board/Kconfig):

    • Guard USART3, SPI2, and RTduino with depends on !SOC_STM32F103C6.
    • Add BSP_USING_SPI1 option (supported on C6).

  4. Flash Optimization Guide:

    • Document optimization steps in README.md and README_zh.md (disabling serial DMA, FinSH symbol descriptions, and reducing shell stack to 2048) to fit standard RT-Thread with interactive FinSH (msh >) within 32KB.
Describe possible alternatives

I have already implemented and verified this solution in the PR #11850

Vorherrschende Sprache
C
Sterne
12.3k
Forks
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Ø Merge
5 T. 16 Std.
Gemergte PRs (30 T.)
27

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