Fix links
@ryanvergel is already working on this.
Since Feb 9, 2023.
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This issue has not been assessed yet.
Description
https://github.com/Xilinx/Vitis-Tutorials/issues/112
The
ref_design <https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/docs/Introduction/ZynqMPSoC-EDT/ref_files/design1>_ for this example provides not only the source code for applications, but also a Makefile to run
through the design generation process. To generate the binaries, run the following command:
Immediate-term Solution: Push a copy of docs (check docs-jp & docs-cn with @mkmatsui ) from the 2022.2 branch to the master branch.
Near-term solution: @RebeccaOHagan & @dasmohana will FAR links that have /tree/master/ to use /tree/version/ instead.
Longer-term solution: Maybe create a package or a release?
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Xilinx/Embedded-Design-Tutorials#52 · 3 comments ·