[proposal] Add vector intrinsics for loading into lane 0 and setting other lanes to 0
Nobody has claimed this yet.
Assessment
- Difficulty
- 5/5
- Estimated time
- Over a week
- Newbie friendliness
- 25/100
Research direction
No file or test is named. Start by reviewing the existing ACLE lane-load intrinsics and the NEON and SVE intrinsic definitions, then compare the proposed signatures with the instruction examples. Done means agreeing on and documenting the intrinsic set and its lane-zero behavior for both architectures.
Written by the indexing model from the issue text.
Description
It would be useful to have vector intrinsics that load lane 0 from memory and set the other elements to zero. E.g.:
int8x16_t vfoo_s8(const int8_t *)→LDR Bn, [Xn]int16x8_t vfoo_s16(const int16_t *)→LDR Hn, [Xn]- ….
The same thing would work for SVE.
GCC does at least optimise something like:
#include <arm_neon.h>
float32x2_t f(float32_t *ptr)
{
float32x2_t vec = {};
vec = vld1_lane_f32(ptr, vec, 0);
vec = vld1_lane_f32(ptr + 2, vec, 1);
return vec;
}
to:
ldr s0, [x0], 8
ld1 {v0.s}[1], [x0]
ret
and LLVM behaves similarly, but that seems a bit indirect.
- Dominant language
- Python
- Stars
- 129
- Forks
- 77
- Avg merge
- 8d 12h
- Merged PRs (30d)
- 2
Getting set up
- No Dockerfile or Docker Compose file
- Has a pull request template
- Read the contributing guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
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