cva6: D-cache data RAM drops its byte enables, so every cache write corrupts the other way

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@oharboe 已经在做这个了。

开始于 2026年11月1日。

  • #4777 来自 @oharboe —— 未关闭

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Issue 类型
缺陷
描述清晰度
描述清楚
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活跃
领域
embedded-iot

调研方向

Start with flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv and trace how wbyteenable reaches fakeram7_128x64; then check the way packing in cva6_hpdcache_subsystem.sv and write behavior in hpdcache_memctrl.sv. Reproduce the two-way set test described in the issue and confirm both lines read back correctly after the fix, including against the upstream RAM wrapper behavior.

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描述

Where: flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv (unchanged
since cb73ed67f; same at 26Q4 ecb3cfdeb), used by designs/asap7/cva6.

What: the wrapper replaces upstream's hpdcache_sram_wbyteenable_1rw with fakeram7_128x64, which has no write
mask, and leaves its wbyteenable input unconnected. cv32a65x packs both ways of a D-cache set into each 64-bit RAM
word (cva6_hpdcache_subsystem.sv: dataWaysPerRamWord = min(2, 128/32) = 2). hpdcache_memctrl.sv replicates the
write data into both 32-bit lanes and selects the way only through the byte enables. With them dropped, every refill and
every store hit, full-word ones included, also overwrites the other way's word at that address. Any program that fills
both ways of a set reads wrong data. The I-cache is not affected (one macro per way, byte enables all ones).

Shown in simulation: upstream cva6 at 3a389af (the commit designs/src/cva6 is based on) with this tree's changed
files, upstream's Verilator testharness, target cv32a65x, Verilator 5.008, behavioural models of the four fakeram7
macros (read on a rising clock with ce_in high, write when we_in, hold otherwise). A 40-line C program writes two
16-byte lines 1 KB apart (one set, both ways), then reads them back alternately and returns the mismatch count:

RTL result cva6 iss_cmp against Spike
upstream's hpdcache_sram_wbyteenable_1rw pass, 525 cycles 100 GPR updates matched
this hpdcache_sram_wbyteenable.sv fail (tohost = 1), 525 cycles first mismatch at c.lw a2, 8(a5): Spike 0x11110002, RTL 0x22220002 (the other way's word)

Consequence: the cva6 netlist the flow builds does not compute correctly; its timing and area are not affected, but
any gate-level or activity-based use of it is.

Possible fixes: a data-RAM macro with a byte write mask connected to wbyteenable, or one macro per way.

主要语言
Verilog
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