MulAddRecFN infinite loops in Chisel elaboration if called with the wrong inputs (expWidth, sigWidth)
Nobody has claimed this yet.
Assessment
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Newbie friendliness
- 35/100
- Issue type
- Bug
- Clarity
- Mostly clear
- Activity status
- Stale
- Tech stack
- scala
- Domain
- embedded-iot
Research direction
Start by reading MulAddRecFN and MulAddRecFN_postMul, then compare their expWidth and sigWidth parameters with the direct rocket.FPUFMAPipe instantiation described in the issue. Trace the elaboration path for expWidth = 52 and sigWidth = 12; done means invalid widths are rejected before elaboration can enter an infinite loop.
Written by the indexing model from the issue text.
Description
There needs to be some enforcement/requirements on the inputs into the hardfloat units (e.g., MulAddRecFN) to catch infinite loops during Chisel elaboration before they occur.
In my particular use-case, the order of the input parameters expWidth and sigWidth had swapped, so I was unknowingly setting expWidth = 52, sigWidth = 12. I am directly instantiating rocket.FPUFMAPipe, which also swapped these parameters, so I never noticed the changes made to hardfloat (the changes to the recoding units was less problematic, since the function name also changed).
I believe the particular infinite loop occurs within MulAddRecFN_postMul, but it's not immediately obvious how.
- Dominant language
- Scala
- Stars
- 393
- Forks
- 110
- PR merge metrics
- No merged PRs in 30d
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