CHERIoT ASR-faulting CSR read counted as retired on WritebackStage=0

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issue の種類
バグ
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明確に書かれている
活発さ
活発
領域
backend

調査の方向性

Start with the reported paths in ibex_wb_stage.sv, ibex_id_stage.sv, and ibex_controller.sv, then compare how CHERIoT faults affect instr_perf_count_id_o and perf_instr_ret_wb_o when WritebackStage=0. Reproduce with the attached csr_asr_minstret.S testcase and compare the mscratch retired count across both configurations. Done means the faulting CSR read does not retire in wb0, matching the expected count of 43.

索引モデルが issue の本文から書いたものです。

説明

Type:Bug

Observed Behavior

In CHERIoT mode with WritebackStage=0, csrr mscratch raises a Permit_Access_System_Registers exception and is included in the retired-instruction count. The other test reads cycle. Only the CSR read differs.

build CSR read retired trap? record (mcause, mtval, rd)
tag_zeros (WritebackStage=1) cycle 37 no 0x0, 0x0, 0x21
tag_zeros (WritebackStage=1) mscratch 43 yes 0x1c, 0x418, 0x0
wb0 (WritebackStage=0) cycle 37 no 0x0, 0x0, 0x24
wb0 (WritebackStage=0) mscratch 44 yes 0x1c, 0x418, 0x0

On the cycle rows the third word is the counter value the test stores.

Expected Behavior

Per the RISC-V Privileged Specification, "Hardware Performance Monitor" (machine.adoc, Zicntr):

The minstret CSR counts the number of instructions the hart has retired.

An instruction that raises an exception does not retire. The wb0 mscratch row should retire 43, the same as tag_zeros.

Steps to reproduce the issue

  • cheriot_enable_i tied on in examples/simple_system/rtl/ibex_simple_system.sv. RV32E=0, SecureIbex=0.
  • tag_zeros: WritebackStage=1. wb0: WritebackStage=0.
  • riscv64-unknown-elf-gcc 13.2.0, -march=rv32imc_zicsr -mabi=ilp32. csr_asr_minstret.S and link.ld are attached.
GCC=riscv64-unknown-elf-gcc
SIM_TAG=/path/to/build_tag_zeros/sim-verilator/Vibex_simple_system
SIM_WB0=/path/to/build_wb0/sim-verilator/Vibex_simple_system

for c in 1 2; do
 $GCC -march=rv32imc_zicsr -mabi=ilp32 -nostdlib -nostartfiles \
 -DCASE=$c -T link.ld \
 -o csr_asr_case$c.elf csr_asr_minstret.S
done

for build in tag_zeros wb0; do
 for c in 1 2; do
 mkdir -p runs/${build}_case$c
 ( cd runs/${build}_case$c && \
 timeout 120 "$SIM_${build^^}" \
 --meminit=ram,csr_asr_case$c.elf -c 20000 > sim.out 2>&1 )
 grep -aE 'Instructions Retired|Cycles' \
 runs/${build}_case$c/ibex_simple_system_pcount.csv
 python3 rec.py runs/${build}_case$c/trace_core_00000000.log
 done
done

tag_zeros case1: Cycles,44 Instructions Retired,37
tag_zeros case2: Cycles,54 Instructions Retired,43
wb0 case1: Cycles,48 Instructions Retired,37
wb0 case2: Cycles,59 Instructions Retired,44

Attached: csr_asr_minstret.S, link.ld, csr_asr_case1.elf, csr_asr_case2.elf, rec.py, and logs/tag_zeros_case1/, logs/tag_zeros_case2/, logs/wb0_case1/, logs/wb0_case2/ (each has pcount.csv and trace.log).

My Environment

EDA tool and version: Verilator (Vibex_simple_system elaborations).

Operating system: Linux 6.8.0-90-generic x86_64.

Version of the Ibex source code: d513671dae09e701ceb6cd732d2da5fb52c13856. The only source change is the cheriot_enable_i tie-off above.

With WritebackStage=0, perf_instr_ret_wb_o is instr_perf_count_id_i & en_wb_i & ~dummy_instr_wb_o & ~(lsu_resp_valid_i & lsu_resp_err_i) (ibex_wb_stage.sv:269). instr_perf_count_id_o (ibex_id_stage.sv:1209) does not include cheriot_asr_err_d (ibex_controller.sv:269). cheriot_wb_err_i is unused (ibex_wb_stage.sv:294).

#2552 (fab0d86) masks CHERIoT faults raised in writeback, and says traps raised in ID are never counted. This fault is csrr mscratch in ID.

testcase.zip

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