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gf180: final report stops with [ERROR PSM-0021] because Via1-Via4 have no RESISTANCE in the tech LEF

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Valutazione

Difficoltà
3/5
Tempo stimato
1-2 giorni
Idoneità per principianti
55/100
Tipo di issue
Bug
Chiarezza
Abbastanza chiara
Stato di attività
Attiva
Ambito
backend, databases

Direzione di ricerca

Start by inspecting flow/platforms/gf180/lef/gf180mcu_5LM_1TM_9K_9t_tech.lef and the GF180MCU PDK resistance data for Via1–Via4 and the other cut layers. Reproduce the failure with the gcd design and the minimal gf180 configuration described in the issue, then run the flow through 6_report. Done means the final report completes with valid via resistance values, or the gf180 configuration skips IR-drop analysis and the flow completes.

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Descrizione

Description

With the gf180 platform's default settings, the flow fails at the final report: IR-drop analysis finds no resistance for the cut layers and stops with PSM-0021, so make exits with an error even though placement, routing and power-grid connectivity are fine.

[INFO PSM-0040] All shapes on net VDD are connected.
[WARNING PSM-0020] Via1 has zero resistance.
[WARNING PSM-0020] Via2 has zero resistance.
[WARNING PSM-0020] Via3 has zero resistance.
[WARNING PSM-0020] Via4 has zero resistance.
[ERROR PSM-0021] Resistance map constains invalid values.
Error: final_report.tcl, 61 PSM-0021

The tech LEF used by default, flow/platforms/gf180/lef/gf180mcu_5LM_1TM_9K_9t_tech.lef, has no RESISTANCE statement in the LAYER Via1 ... LAYER Via4 blocks. This is still the case on current master.

To reproduce

ORFS commit c06bf3c (2026-06-16). There is no gcd config for gf180 at that commit, so we used flow/designs/src/gcd/gcd.v with a minimal config:

export PLATFORM          = gf180
export DESIGN_NAME       = gcd
export VERILOG_FILES     = $(DESIGN_HOME)/src/gcd/gcd.v
export SDC_FILE          = <a 20 ns clock on clk>
export CORE_UTILIZATION  = 40
export PLACE_DENSITY     = 0.60

make DESIGN_CONFIG=... CORNER=TC runs to 6_report and fails there with the lines above (about 4 minutes on 8 cores).

Workaround we use

Setting PWR_NETS_VOLTAGES = and GND_NETS_VOLTAGES = (empty) skips the IR-drop analysis, and the flow completes; we check power-grid connectivity separately with check_power_grid.

Suggested fix

Add RESISTANCE values for Via1-Via4 (and the other cut layers) to the gf180 tech LEFs, taken from the GF180MCU PDK; or have the gf180 platform config skip IR-drop analysis by default until they are there.

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Verilog
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