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FP16 simulation execution context + FP32-accumulating LayerNorm lowering rule (variance overflow repro)

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#1,281 1 comentario 0 reacciones 0 asignados Ver en GitHub

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Evaluación

Dificultad
5/5
Tiempo estimado
Más de una semana
Aptitud para principiantes
35/100
Tipo de issue
Nueva funcionalidad
Claridad
Bastante claro
Estado de actividad
Activo
Stack tecnológico
kotlin
Área
compilers, machine-learning

Línea de trabajo

Start by locating Fp16SimulationExecutionContext or the DirectCpuExecutionContext option and the Fp16Codec, then identify the reduction tests and the layerNorm lowering rule in skainet-compile-hlo. Reproduce the overflow on the JVM with a synthetic [1500,1280] input, and check that the FP16 lowering emits an F32 variance reduction with a TraceEvent naming the rule. Done also includes the documentation page and, when an FP16 target exists, passing the IREE parity harness (#1148).

Escrito por el modelo de indexación a partir del texto del issue.

Descripción

compiler enhancement skill:numerics

Context

An FP16 LayerNorm computes variance as a mean over 1280 squared, centred activations. For real Whisper encoder activations the sum exceeds the FP16 maximum before the division, variance becomes +Inf, rsqrt becomes 0, and the block silently emits zeros for those frames — 6 of 1500 frames in the measured case, enough to drop encoder cosine from 0.9999 to 0.968. The fix on the LiteRT side was a graph rewrite ((0.25·δ)² · 16) because the runtime offered no lever.

SKaiNET will meet the same bug the moment an FP16 GPU or NPU lowering exists. It should be reproducible on a desktop CPU before that, so the lowering rule (accumulate variance in FP32, or apply the rescale) can be written and regression-tested against a known-failing input.

Scope

  • Fp16SimulationExecutionContext (or a DirectCpuExecutionContext option): after every op, round the output through Fp16Codec (round-to-nearest-even, overflow to ±Inf, gradual underflow) — storage-only simulation. A second mode also rounds accumulators inside reductions (sum/mean/variance/matmul) to model true half-precision arithmetic.
  • A regression test with a synthetic [1500,1280] input scaled so that naive FP16 variance overflows, asserting +Inf under accumulate-in-half and a finite, correct value under the FP32-accumulate lowering.
  • layerNorm lowering rule for FP16 targets in skainet-compile-hlo: variance reduction in F32 (or the documented rescale), with a TraceEvent naming which rule fired.
  • Docs: an explanation page on narrow-float numerics pitfalls with this as the worked example.

Acceptance

  • The overflow reproduces in a unit test on a JVM with no GPU.
  • The StableHLO emitted for an FP16 LayerNorm shows the F32 reduction, and the test passes through the IREE parity harness (#1148) when an FP16 target exists.

Related

  • #884, #885 — narrow-float layer and FP16 kernels
  • #1148 — parity acceptance
Lenguaje dominante
Kotlin
Estrellas
52
Forks
15
Merge medio
1 d 15 h
PR fusionados (30 d)
36

Preparar el entorno

Primeros pasos

  1. Lee el issue completo y luego la guía de contribución del proyecto.
  2. Comenta en el issue que vas a ocuparte — evita que dos personas hagan lo mismo.
  3. Haz un fork del repositorio y trabaja en una rama.
  4. Abre un pull request que haga referencia al número del issue.

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