QSFP/I2C: Ability to request protocol resets
@Aaron-Hartwig 已经在做这个了。
开始于 2023年11月17日。
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描述
Per SFF-8636 section 5.2.2:
Synchronization issues may cause the master and slave state machines to disagree on the specific bit location currently being transferred, the type of operation or even if an operation is in progress. The 2-wire interface protocol has no explicitly defined reset mechanism. The following procedure may force completion of the current operation and cause the slave to release SDA.
a) The master shall provide up to nine SCL clock cycles (drive low, then high) to the slave.
b) The master shall monitor SDA while SCL is high on each cycle.
c) If the slave releases SDA, it will be high and the master shall initiate a START condition.
d) If SDA remains low after a full nine clock cycles the protocol reset has failed.
The I2CCore::Operation enum should be expanded to accommodate a ProtocolReset variant. Per the above, the I2CCore state machine would need to clock out 9 cycles while reading SDA. If SDA is or transitions high during that period, the peripheral has released the bus. If not, the protocol reset has failed.
From the QsfpModuleController perspective, we will need to decide when this should be done. All our module I2C busses are point to point, so we should never get an unexpected NACK. In the case we do receive one, perhaps we should execute a protocol reset?
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