Modeling subregister aliasing

首先阅读当前 regalloc2 API 中与 PRegs、物理寄存器类和 clobber 集合相关的内容，然后将其与 LLVM 的 register-units 和 subregister 模型进行比较。完成的标准是确定是否能够表示别名，或记录一种 allocator 外部支持的方法，例如固定 constraints、显式 moves 或拆分 live-range。

I’m experimenting with using regalloc2 for a cranelift backend targeting a old Z80 8-bit CPU with hierarchical registers —
where two small registers can form one larger register, and vice versa:

B + C = BC (16-bit)
D + E = DE (16-bit)
H + L = HL (16-bit)

Here’s the challenge:

Some 16-bit instructions can use either BC or DE.
When BC is used, both B and C become clobbered.
When DE is used, D and E are clobbered instead.

The 8-bit registers are individually addressable, but they also participate in 16-bit operations as pairs.

The problem is that regalloc2 assumes all physical registers in a class are disjoint,
and clobber sets must be fixed before allocation.
That makes it unclear how to express a relationship like “BC aliases both B and C” or “writing BC invalidates B and C.”

LLVM handles this using register units and subregisters, where overlapping registers share “register units”
and the allocator tracks partial definitions and interference on that level.
regalloc2, however, currently has no notion of aliasing or register overlap.

So I’m wondering:

Is there any way to model such subregister aliasing with the current regalloc2 API?

Would it make sense to support aliasing PRegs or register subsets (similar to LLVM’s register units / subregister indices)?

Or is the current expectation that these aliasing relationships be handled entirely outside the allocator,
e.g. by inserting explicit moves, using fixed constraints, or splitting live ranges manually?