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risc-v vector v1.0 support

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#4,050 10 則留言 1 個 reaction 已指派 0 人 在 GitHub 檢視

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評估

難度
5/5
預估耗時
一週以上
新手友好度
25/100
Issue 類型
功能
描述清晰度
需要釐清
活躍度
停滯
技術堆疊
c
領域
performance

研究方向

從 issue 中提到的 RVV kernel 開始,尤其是 symv_L_rvv.c 第 96 行和 gemm_tcopy_8_rvv.c 第 84 行,並檢視 x280 特定的編譯器旗標。將目前的 GEMM_UNROLL_N_SHIFT 設定與不同的 VLEN 假設進行比較,並考量 tail/mask 策略以及指令順序相容性。需要針對不同 VLEN 值和 CPU 上的 RVV 1.0 相容性達成一致的實作範圍,才能視為完成。

由索引模型根據 Issue 內容生成。

描述

The discussions in #4049 inspire me to creat an issue for further discussions.
Differ from commercial ISAs, which have a clear development plan, the total amount of products supporting rvv may be large. Optimization for all individual products may lead to code bloat, and is contrary to the purpose of the vector isa, which is expected to be length-adaptive.
Until now the intrinsic spec of rvv 1.0 is stable enough to develop codes, and the support of rvv 1.0 has been fully submitted to openblas, based on sifive x280, an in-order cpu with vlen=512.
Would it be better to do more development, based on this x280 version? The final destination may be the compatibility in different vlen, instruction execution order, tail/mask policy. Of course the pursuing of compatibility may lead to suboptimum performance, a balance have to be considered.
There are some cpu specified features in kernels of x280 and may lead to incorrect results in other cpus. List as following

  1. Architecture specified cflags, such as -riscv-v-vector-bits-min=512 and -ffast-math.
  2. Changing vl in a loop, leading to tail cleared without tail undisturbed setted. Such as vl = VSETVL(k); in symv_L_rvv.c, line 96.
  3. Set vl by immediate value under the assumption of vlen=512. Such as size_t vl = 8; in gemm_tcopy_8_rvv.c, line 84.

In addition to above, the registers tiling in gemm of different vlen should be considered. Now we set GEMM_UNROLL_N_SHIFT 8, which may waste other vector registers. 12 or 14 may be better?

主要語言
C
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平均合併
1 天 6 小時
30 天內合併 PR
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從這裡開始

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  3. Fork 儲存庫,在一個分支上完成修改。
  4. 送出 Pull Request,並在描述裡引用這個 Issue 編號。

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