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Refactor ImproveMemoryOps around shared, read-only address analysis

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#3,990 0 bình luận 2 reaction 0 người được giao Xem trên GitHub

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cpp
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compilers

Hướng nghiên cứu

Start by locating ImproveMemoryOps and GatherCoalescePass, then read the existing gather/scatter baseline tests and benchmarks mentioned in the issue. The first PR is to add a read-only access decoder and base/offset analysis that feeds existing emission. It is done when assembly and diagnostics remain unchanged; the issue does not name specific source or test file paths.

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Mô tả

Code Cleanups Codegen Performance

ImproveMemoryOps mixes address recognition, legality checks, target decisions, and IR construction. Some matchers create instructions before matching succeeds, and address analysis overlaps with GatherCoalescePass. Width, extension, and overflow assumptions are spread across several helpers, making changes difficult to audit.

The goal is an incremental refactoring that preserves existing performance and correctness, then enables targeted improvements using the gather/scatter baseline tests and benchmarks already prepared.

Proposed plan

  1. Introduce a shared, read-only access description.
    Describe the original operation, uniform base or general varying pointers, offsets, arithmetic widths, extension operations, scale, displacement, lane pattern, mask, alignment, address space, and source location. Start with existing pseudo-call forms, including the prefetch paths handled by this pass. Failed matching must leave IR unchanged; unknown cases retain a valid fallback.

  2. Separate analysis, legality, selection, and emission.
    Initially feed the new analysis into existing emitters and retain current target choices. Migrate base/offset recovery, constant factoring, recovery of additional constants after intervening passes, broadcast, forward/reverse linear access, and known-mask simplification in small changes. Preserve repeated optimization when a replacement exposes another opportunity.

  3. Make address-equivalence and footprint checks explicit.
    Audit narrowing, arithmetic across extensions, and overflow-flag propagation. Choosing a 32-bit gather index must preserve the effective address, including hardware scale and displacement. Broadcast and wider-load transformations must preserve inactive-lane fault behavior. Store transformations must preserve active-lane values and overlap semantics.

  4. Deliver width and scale improvements separately from structural changes.
    Recognize shl as well as mul, handle scale plus field displacement, and use range/known-bit information for narrow unsigned indices. Allow 32-bit hardware indices under either addressing mode when proven equivalent; otherwise retain 64-bit indices. Initial targets are #1256, #1531, and #1581.

  5. Integrate with post-inline cleanup and late lowering.
    Coordinate with #3808 so address information survives the final application inliner. Carry the original index and extension explicitly when later IR analysis cannot recover them reliably. Account for builtin lifetime, expansion after lowering, subsequent cleanup, and warning locations. Validate normal and deferred-inlining configurations independently.

  6. Reuse the analysis for local patterns and grouped coalescing.
    Extend exact-footprint repeated-address and permutation cases, then migrate GatherCoalescePass. Follow-on changes can support non-factored gathers on hardware-gather targets, more element types, equivalent address expressions, and alias-aware grouping. This provides the path toward #304/#330 and related layout cases.

Related work and boundaries

  • Land #3984/#3985 correctness fixes separately before dependent transformations.
  • Split #3983 into independent attribute fixes and representation/pipeline work.
  • Keep aggregate-copy packing, adjacent scalar-store combining, and masked-byte-store improvements as follow-on changes for #2778, #2720, #2943, #2308, and #2901/#2899.
  • Broad LLVM-intrinsic replacement and a full target cost model can follow once the analysis and migration are validated.

Validation and acceptance

  • Structural changes preserve normalized assembly and diagnostics.
  • Optimization changes document intended differences and update the corresponding issue-test expectations.
  • Exercise guard pages, all-off/sparse/tail masks, signed and unsigned indices, overflow boundaries, aliasing, duplicate scatter addresses, both addressing modes, wide gangs, and relevant disable options.
  • Run LLVM 20–24 checks, existing functional/lit suites, and external-corpus comparisons.
  • Compare warmed, repeated whole-kernel timings against both the preceding revision and the fixed baseline; investigate reproducible slowdowns below the dashboard threshold.
  • Track compile time, code size, and spills. Use native hardware for performance decisions; SDE supplies correctness and instruction evidence.

First PR: introduce the access decoder and read-only base/offset analysis feeding existing emission, with unchanged assembly and diagnostics.

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C++
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