vhda/verilog_systemverilog.vim

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Verilog/SystemVerilog Syntax and Omni-completion

Stars: 424
Forks: 93
Open beginner issues: 0
Indexed issues: 28

Dominant language: Vim Script
License: No license data
Last GitHub push: Aug 3, 2026
Latest indexed: Sep 20, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: No beginner labels indexed
PR merge metrics: No merged PRs in 30d

Beginner friendly Everything

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28 open issues indexed

indent lost after endcase of randcase block Open

Difficulty 3/5 1-2 days Newbie friendliness 50/100

vhda/verilog_systemverilog.vim#250 · 1 comment · Opened Sep 15, 2025
vim become very slow when there is a long define Open

vhda/verilog_systemverilog.vim#243 · 6 comments · 1 reaction · 1 assignee · Opened Aug 3, 2024
folding error when using extern function/task with argument Open

Difficulty 3/5 1-2 days Newbie friendliness 45/100

vhda/verilog_systemverilog.vim#242 · 1 comment · 1 reaction · Opened May 12, 2024
tagbar need add other labels Open

vhda/verilog_systemverilog.vim#241 · 2 comments · 1 assignee · Opened May 11, 2024
UVM highlight? Open

Difficulty 3/5 1-2 days Newbie friendliness 45/100

vhda/verilog_systemverilog.vim#240 · Opened May 10, 2024
Indent conflict between modport and clocking Open

Difficulty 2/5 1-3 hours Newbie friendliness 45/100

vhda/verilog_systemverilog.vim#238 · Opened Mar 26, 2024
Folding works on some files Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

vhda/verilog_systemverilog.vim#235 · 3 comments · Opened Jan 22, 2024
[BUG] macros breaking indentation Open

Difficulty 3/5 1-2 days Newbie friendliness 45/100

vhda/verilog_systemverilog.vim#231 · 18 comments · Opened Jun 30, 2023
Intendation is slow when inserting a new line into the thousands signal interface Open

Difficulty 3/5 1-2 days Newbie friendliness 35/100

vhda/verilog_systemverilog.vim#229 · 3 comments · Opened Mar 6, 2023
Undefined variable: g:verilog_syntax Open

Difficulty 3/5 1-2 days Newbie friendliness 35/100

vhda/verilog_systemverilog.vim#228 · 7 comments · Opened Mar 4, 2023
Typedef classes are not handled by Omnicomplete Open

vhda/verilog_systemverilog.vim#225 · 3 comments · 1 assignee · Opened Feb 15, 2023
System Verilog struct and class member auto completion Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

vhda/verilog_systemverilog.vim#207 · 3 comments · Opened May 5, 2021
Rainbow 'begin/end' Support Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

vhda/verilog_systemverilog.vim#204 · 8 comments · Opened Feb 28, 2021
Demo Request Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

vhda/verilog_systemverilog.vim#199 · 2 comments · Opened Jun 11, 2020
Highlight issue with systemverilog: if : else if : else/else if Open

Difficulty 3/5 1-2 days Newbie friendliness 32/100

vhda/verilog_systemverilog.vim#196 · Opened May 8, 2020
Unhighlighted pin after linebreak (\n) Open

Difficulty 2/5 1-3 hours Newbie friendliness 35/100

vhda/verilog_systemverilog.vim#191 · 4 comments · Opened Mar 13, 2020
Include context description in omni completion Open

enhancement omni

vhda/verilog_systemverilog.vim#182 · 1 assignee · Opened Mar 29, 2019
Optimize syntax according to file extension Open

enhancement syntax

vhda/verilog_systemverilog.vim#154 · 1 assignee · Opened Oct 11, 2017
Doesn't work for systemverilog struct Open

enhancement

vhda/verilog_systemverilog.vim#150 · 9 comments · 1 assignee · Opened Oct 5, 2017
Indent define blocks Open

enhancement indent

vhda/verilog_systemverilog.vim#104 · 3 comments · 1 assignee · Opened May 24, 2016
Preprocessor statements break indentation. Open

bug indent

vhda/verilog_systemverilog.vim#103 · 3 comments · 1 assignee · Opened May 19, 2016
Special instance indentation support Open

enhancement indent

vhda/verilog_systemverilog.vim#102 · 8 comments · 1 assignee · Opened May 18, 2016
Review perfomance impact when reading configuration variables Open

vhda/verilog_systemverilog.vim#96 · 1 assignee · Opened May 10, 2016
Consider supporting Syntastic Open

enhancement

vhda/verilog_systemverilog.vim#79 · 1 assignee · Opened Apr 12, 2016
Incorrect indentation of multi-line condition. Open

bug indent

vhda/verilog_systemverilog.vim#70 · 8 comments · 1 assignee · Opened Mar 8, 2016
Syntax highlight is wrong inside named and nested blocks Open

bug syntax

vhda/verilog_systemverilog.vim#63 · 1 comment · 1 assignee · Opened Feb 24, 2016
Omni-completion does not work in non-hierarchical references Open

bug omni

vhda/verilog_systemverilog.vim#50 · 1 assignee · Opened Jan 22, 2016
Improve syntax performance Open

enhancement syntax

vhda/verilog_systemverilog.vim#42 · 1 comment · 1 assignee · Opened Nov 13, 2015

vhda/verilog_systemverilog.vim

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