[Query] Max Instruction Size for riscv64
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Assessment
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Newbie friendliness
- 25/100
Research direction
Start by locating the architecture-specific MaxInstructionSize cases in the MIEngine code and compare the existing ARM64 handling with the riscv64 debugging support described in the issue. Confirm the expected value against the MIEngine debugger integration and riscv64 instruction behavior; done means the value is established and the relevant architecture support can be updated.
Written by the indexing model from the issue text.
Description
Hello, I have a query. I am a developer for Tizen SDK for Visual Studio. For supporting debugging of riscv64 architecture in VS, we are modifying miengine project. While adding code, we found a variable named MaxInstructionSize for each architecture in miengine code.
Example:
case TargetArchitecture.ARM64:
MaxInstructionSize = 8;
Is64BitArch = true;
break;
What might be the MaxInstructionSize for riscv64?
- Dominant language
- C#
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- 4d 14h
- Merged PRs (30d)
- 3
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