SIGILL on SME-only AArch64 CPUs caused by SVE auto-vectorization in SME interleave wrappers

interleave_indirect-sve.cpp、indirect-interleaves/list-sve.hpp、そして sme_interleave*.hpp の実装から始め、提示された SCons コマンドと最小プログラムを使って再現します。SME の特殊化がどのように SVE ソースグループに入るかを追跡し、指定された SME-only CPU 上で生成された命令を検証します。SME2 GEMM パスが SIGILL なしで実行され、妥当な SME2 カーネル選択が維持されれば完了です。

Summary

An ACL multi-ISA build selects an SME2 FP16 GEMM kernel on a CPU that supports SME/SME2 but does not expose non-streaming SVE. The SME2 kernel selection itself appears valid.
However, the SME input-interleave specialization is instantiated from interleave_indirect-sve.cpp. That translation unit includes indirect-interleaves/list-sve.hpp, which also pulls in the sme_interleave*.hpp implementations, and is compiled as part of the SVE source group with an SVE-enabled -march.
As a result, GCC auto-vectorizes the wrapper's ordinary C++ with non-streaming SVE instructions, raising SIGILL.

Environment

• AArch64 Linux, GCC 11.4.0, binutils 2.38, SCons 4.0.1
• /proc/cpuinfo Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 asimddp sha512 asimdfhm dit uscat ilrcpc flagm sb dcpodp flagm2 frint i8mm bf16 ecv afp sme smei16i64 smef64f64 smei8i32 smef16f32 smeb16f32 smef32f32 ebf16 sme2 sme2p1 smei16i32 smebi32i32 smeb16b16 smef16f16
• Build: scons -j14 Werror=0 debug=0 neon=1 opencl=0 os=linux arch=armv8.6-a-sve2-sme2 multi_isa=1 build=native cppthreads=1 openmp=0 examples=0

Minimal code to reproduce

#include <arm_compute/core/TensorInfo.h>
#include <arm_compute/core/Types.h>
#include <arm_compute/runtime/NEON/NEFunctions.h>
#include <arm_compute/runtime/Tensor.h>

using namespace arm_compute;

int main()
{
    const unsigned int M = 128, N = 128, K = 128;
    Tensor a, b, c;
    a.allocator()->init(TensorInfo(TensorShape(K, M), 1, DataType::F16));
    b.allocator()->init(TensorInfo(TensorShape(N, K), 1, DataType::F16));
    c.allocator()->init(TensorInfo(TensorShape(N, M), 1, DataType::F16));
    a.allocator()->allocate();
    b.allocator()->allocate();
    c.allocator()->allocate();

    NEGEMM gemm;
    gemm.configure(&a, &b, nullptr, &c, 1.0f, 0.0f);
    gemm.run();
    return 0;
}

Compile and run:

g++ -std=c++17 -O2 -I. -Iinclude repro.cpp -Lbuild -larm_compute -Wl,-rpath,$PWD/build -lpthread -ldl -o repro
./repro

Backtrace:

#0  0x0000fffff7d6cf5c in void arm_gemm::Interleave<1u, 2u, (arm_gemm::VLType)2, half, half>(half*, half const*, unsigned long, unsigned int, unsigned int, unsigned int, unsigned int, bool, int) ()
#1  0x0000fffff7c72840 in arm_gemm::GemmInterleaved<arm_gemm::cls_sme2_interleaved_nomerge_fp16fp32fp16_mopa_1VLx4VL, half, half, half, arm_gemm::Nothing, false, false, false, true>::execute_common(arm_gemm::NDCoordinate<6u> const&, arm_gemm::NDCoordinate<6u> const&, int, arm_gemm::GemmArrays<half, half, half>&) ()
#2  0x0000fffff77d0d4c in arm_compute::cpu::kernel::CpuGemmAssemblyWrapperKernel<half, half, half>::run_nd(arm_compute::Window const&, arm_compute::ThreadInfo const&, arm_compute::Window const&) ()

Disassembly:

   0xfffff7d6cf54 <_ZN8arm_gemm10InterleaveILj1ELj2ELNS_6VLTypeE2EDhDhEEvPT3_PKT2_mjjjjbi+180>: sub     x27, x29, #0x18
   0xfffff7d6cf58 <_ZN8arm_gemm10InterleaveILj1ELj2ELNS_6VLTypeE2EDhDhEEvPT3_PKT2_mjjjjbi+184>: mov     x21, x20
=> 0xfffff7d6cf5c <_ZN8arm_gemm10InterleaveILj1ELj2ELNS_6VLTypeE2EDhDhEEvPT3_PKT2_mjjjjbi+188>: uqdecd  x21