Intel Panther Lake PMU support

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Valutazione

Difficoltà
3/5
Tempo stimato
1-2 giorni
Idoneità per principianti
55/100
Tipo di issue
Funzionalità
Chiarezza
Abbastanza chiara
Stato di attività
Attiva
Stack tecnologico
cpp, linux
Ambito
backend, operating-systems

Direzione di ricerca

Start with src/PerfCounters_x86.h at compute_cpu_microarch(), where the unknown Intel family 6 model 0xcc is reported, and inspect the attached patch and diagnostics for the proposed Panther Lake settings. Check how existing Intel microarchitectures define rcb_cntr_event, PMU_TICKS_RCB, and skid allowances. Done means rr can record on Panther Lake with the documented conditional-branch event encoding and the appropriate P-core and E-core settings.

Scritto dal modello di indicizzazione a partire dal testo della issue.

Descrizione

Hi rr team. I built rr from commit 116719af0a37781ef8d2f6d6d4c4fbcd769a31f1 on a new
Intel Core Ultra X9 388H laptop. But trying to record fails with:

$ rr record ls
[FATAL src/PerfCounters_x86.h:190:compute_cpu_microarch()] Intel CPU family 0x6 model 0xcc unknown

I asked ChatGPT to prepare a fix for me, and it came up with the attached patch which has been working fine for me so far:
rr-panther-lake-116719af.patch

I also had it gather details of my laptop that my be helpful to you, and here they are:
rr-panther-lake-diagnostics.txt

In the usual ChatGPT way, it wanted to send you a very verbose message. I've cut it down to essentials:

Hardware reported by lshw

Product: Intel(R) Core(TM) Ultra X9 388H
Family: 6
Model: 204 decimal / 0xcc
Stepping: 2 (lshw version: 6.204.2)
Microcode: 281, as reported by lshw
Enabled cores / hardware threads: 16 / 16

Intel identifies this product as Panther Lake, with 4 P-cores, 8 E-cores and 4 low-power E-cores. The relevant microarchitectures are Cougar Cove for the P-cores and Darkmont for the E-cores.

Panther Lake's documented conditional-branch event encoding differs from both Arrow Lake and Skymont. Intel's event data specifies
BR_INST_RETIRED.COND with EventCode=0xc4, UMask=0x07 and UMaskExt=0x00 for both Cougar Cove and Darkmont. In rr's existing table convention, this corresponds to rcb_cntr_event=0x5107c4.

Intel's mapfile explicitly maps GenuineIntel-6-CC to these Cougar Cove and Darkmont event files.

The patch preserves retired-conditional-branch tick semantics (PMU_TICKS_RCB). It uses initial skid allowances of 125 for Panther Lake P-cores and 100 for Darkmont, borrowed from the corresponding preceding rr configurations.

Lingua principale
C++
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