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amdgpu unified RAS: GFX correctable errors aggregated by MP5 firmware are dropped on MI450 (no GFX error count, no CPER)

Aperta
#239 0 commenti 0 reazioni 0 assegnatari Vedi su GitHub

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Dal 11/10/2026.

  • #236 di @tpatward-amd — aperta

Valutazione

Difficoltà
4/5
Tempo stimato
3-5 giorni
Idoneità per principianti
28/100
Tipo di issue
Bug
Chiarezza
Specificata chiaramente
Stato di attività
Attiva
Stack tecnologico
c

Direzione di ricerca

Start in drivers/gpu/drm/amd/ras/core/aca_v5_0.c with aca_hwip_maps[], aca_get_bank_aca_block() and ras_aca_parse_bank(), then follow the caller amdgpu_ras_mce_notifier_v5() to see where the bank is dropped on -ENODATA. Done means an MP5 bank carrying ErrorCodeExt 0x3E with SyndV and ErrorInformation 0x18 is attributed to GFX, classified from the copied STATUS, counted as at least one error, and encoded as CPER, while other MP5 errors stay unattributed. Check for an existing ACA test or simulation path before changing behaviour.

Scritto dal modello di indicizzazione a partire dal testo della issue.

Descrizione

Symptom

On an AMD Instinct MI450 system (gfx 12.1, ACA v5, flex MCA) with unified RAS (drivers/gpu/drm/amd/ras) enabled, a correctable GFX MCA error is decoded and logged by the x86 MCE core, but amdgpu does nothing with it:

  • the record does not appear in the amdgpu ACA log,
  • the GFX correctable error count does not change,
  • no runtime CPER is produced, so in-band tools that read CPER records through the RAS command interface see no error.

A record from a block that is mapped (for example PCS_XGMI) is logged, counted and encoded as a CPER in the same setup.

Affected
  • ASIC/IP: MI450 class parts using ACA v5 (drivers/gpu/drm/amd/ras/core/aca_v5_0.c).
  • Flow: MCE notifier path amdgpu_ras_mce_notifier_v5() -> ras_aca_parse_bank() -> ACA log / log ring -> CPER.
  • Error class: GFX MCA errors that platform firmware reports through the MP5 MCA bank.
Example record (as logged by the MCE core)
STATUS 0x9c200000003e0109  (Val|En|MiscV|AddrV|SyndV, ErrorCodeExt 0x3E)
ADDR   0x000000000000002e
MISC0  0xd018000000000000  (ErrCnt 0)
IPID   0x0002100136430404  (HWID 0x01, McaType 0x2 = SMCA MP5; socket 4, die 1)
SYND   0x0000000042010018  (ErrorInformation 0x1_0018 = aggregated error)
Root cause

The host never sees the GFX MCA bank itself. MP5 firmware polls the GFX MCA banks and copies an error into its own MP5 bank. The copied STATUS has ErrorCodeExt 0x3E (firmware logged), SYND.ErrorInformation[15:0] is 0x18 (aggregated error), and MISC0.ErrCnt is copied too. It can be 0.

aca_hwip_maps[] in ras/core/aca_v5_0.c has no entry for HWID 0x01 / McaType 0x2. aca_get_bank_aca_block() finds no block for the bank and ras_aca_parse_bank() returns -ENODATA. amdgpu_ras_mce_notifier_v5() then returns before it queues the bank, so there is no ACA log entry, no GFX count and nothing for CPER encoding. Even if the bank were mapped, the default MCE parse counts a CE as MISC0.ErrCnt, so a copy with ErrCnt 0 would be counted as zero errors.

Expected

An MP5 bank that carries both aggregation markers (ErrorCodeExt 0x3E with SyndV, and ErrorInformation[15:0] 0x18) should be attributed to the GFX block. It should be classified from the copied STATUS (UC/PCC/TCC -> UE, otherwise CE) and counted as at least one error. MP5's own errors (for example SMN timeout 0x2 or DMA error 0x19) should stay unattributed.

Lingua principale
C
Stelle
470
Fork
150
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