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Ground plane discontinuity under switching regulators (2-layer board)

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Valutazione

Difficoltà
4/5
Tempo stimato
3-5 giorni
Idoneità per principianti
42/100
Tipo di issue
Bug
Chiarezza
Abbastanza chiara
Stato di attività
Tranquilla
Ambito
embedded-iot

Direzione di ricerca

Start by opening the Okapi PCB layout and inspecting the switching-loop areas around U1, U2, and U4. Check bottom-pour continuity, output-capacitor ground returns, exposed-pad stitching, and routing near sensitive analog signals. Done means each listed layout condition has been reviewed and corrected where needed, with any remaining respin or EMI concerns documented.

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Descrizione

bug

Summary

The Okapi board is a 2-layer PCB. Switching regulators (LT3652 solar charger, TPS62822 step-down, TLV61220 boost) require a continuous, low-inductance ground plane under and around their switching nodes to control EMI and maintain loop stability. On a 2-layer board, the bottom copper layer typically serves as the ground plane, but routing traces through that layer creates interruptions that force return currents to take long, high-inductance paths.

Specific concerns

LT3652 (U4, solar charger):

  • High switching currents (up to ~1.5 A) flow in the LT3652 switching loop: U4 SW pin → inductor → output cap → GND → U4 GND
  • Any trace routing that interrupts the bottom copper under this loop increases parasitic inductance, increasing output voltage ripple and EMI
  • The LT3652 evaluation board (DC1489A) uses an unbroken copper pour on the bottom layer directly under the IC and inductor

TPS62822 (U2, 3V3_AUX step-down):

  • Same concern: the SW node, inductor, and output capacitor form a high-dI/dt loop that needs a solid ground reference
  • TI layout guidelines for TPS6282x explicitly state: place input and output caps and the inductor in a tight cluster, with the exposed pad via stitched to the ground plane

TLV61220 (U1, boost converter):

  • Boost converters are particularly sensitive to poor ground plane due to the high-frequency current pulses on the input side
  • TI application note SLVA344 shows the critical ground pour must be uninterrupted

On a 2-layer board this is hard to fix without a respin

Unlike a 4-layer board where a dedicated internal ground plane is always available, a 2-layer board must use the bottom layer as ground — but this conflicts with routing needs. Options:

  1. Minimize top-layer crossing traces under regulators: Keep all signal routing away from regulator switching loop areas; use the bottom layer only for ground fill in those zones.
  2. Use copper pours with thermal reliefs disabled in the switcher areas on both layers; use stitching vias liberally.
  3. Route sensitive analog signals (ADC inputs, crystal, AREF) far from switcher switching nodes — especially the LT3652 SW node which sees the full battery/solar voltage.
  4. Add a common-mode ferrite on the 5V output of U3 (if applicable) if radiated EMI is measured to be a problem.
  5. Long-term: consider moving to a 4-layer stackup for future board revisions. Cost is modest at low volumes; the benefit in ground plane quality, EMI, and layout flexibility is significant.

Immediate action (current board revision)

Review the layout around each switcher's switching loop and confirm:

  • The bottom copper pour is continuous (no routing traces crossing under the IC or inductor)
  • Output capacitor GND returns connect directly to the ground pour, not via a long trace
  • The exposed pad (EP) of each switching regulator is via-stitched to the bottom ground pour with ≥4 vias

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  3. Fai un fork del repository e lavora su un branch.
  4. Apri una pull request che faccia riferimento al numero della issue.

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