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fbgemm-xpu: fuse INT4/INT8 quantized lookup across tables into fewer kernel launches

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Assessment

Difficulty
5/5
Estimated time
Over a week
Newbie friendliness
25/100
Issue type
Feature
Clarity
Clearly specified
Activity status
Active
Tech stack
cpp, pytorch

Research direction

Read embedding_forward_quantized.cpp and embedding_forward_quantized_kernel_template.h to trace the per-table INT4 and INT8 launches, then review the upstream CUDA launcher for its table dimension. Run test_int_nbit_lookup.py to check CPU/XPU parity and single-table behavior. Done means launches stop scaling with table count, required mixed-type coverage is added, benchmarks cover 1–128 tables, and the header comment and package docs are updated.

Written by the indexing model from the issue text.

Description

The XPU quantized lookup (int_nbit_split_embedding_codegen_lookup_function) submits one SYCL kernel per embedding table, so launch overhead grows linearly with table count. Process several tables per launch instead.

Background

Current behavior

Acceptance criteria

  • Launches no longer scale with table count. Use one per weight type, or one shared launch.
  • CPU/XPU parity for INT4 and INT8.
  • Mixed INT4/INT8 tables are tested, if the design supports them.
  • No single-table regression.
  • Benchmark results for 1–128 tables, using the same BMG methodology as #132.
  • The header comment and package docs are updated.
Dominant language
C++
Stars
5
Forks
9
Avg merge
3d 10h
Merged PRs (30d)
11

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