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check_axi_stream not detecting errros in 5.0.0.dev6

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#1,127 4 comentarios 0 reacciones 0 asignados Ver en GitHub

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Evaluación

Dificultad
4/5
Tiempo estimado
3-5 días
Aptitud para principiantes
35/100
Tipo de issue
Error
Claridad
Bien especificado
Estado de actividad
Estancado
Área
testing-qa

Línea de trabajo

The reproduction identifies the failing call in <root>/test/base/olo_base_arb_wrr/olo_base_arb_wrr_tb.vhd at line 138 and the test command in <root>/sim. Start by running python3 run.py *arb_wrr* with vunit_hdl 5.0.0.dev6 and compare the result with 4.7.0. Done means the 5.0.0.dev6 run detects the data mismatch and fails as expected.

Escrito por el modelo de indexación a partir del texto del issue.

Descripción

Enhancement

I noticed that in 5.0.0.dev6 check_axi_stream() does not detect data mismatches. Testbenches that worked correctly and actually checked results in 5.0.0.dev6 seem to no more check results and always pass.

IMO this is very CRITICAL. If VUnit does fail due to a bug, this is unhandy but it does not lead to buggy designs passing verification - the problem is detected and a solution can be found. Here the situation is that VUnit does NOT FAIL even if bugs are present. Even worse - testbenches that used to work correctly in the past and in which developers may trust will not do their checks and always succeed. IMO this problem should be tackled better sooner than later.

I have created a reproduction setup here:
https://github.com/open-logic/open-logic/tree/debug/vunit-check-axi-stream-issue

The incorrectly working check_axi_stream() call is in /test/base/olo_base_arb_wrr/olo_base_arb_wrr_tb.vhd on line 138

I am working with ghdl 5.0.1 but I believe the simulator should not play a role

How to reproduce:

  1. Checkout the branch mentioned above
  2. Ensure vunit_hdl 5.0.0.dev6 is installed
  3. Navigate to /sim
  4. Execute python3 run.py *arb_wrr* --> This will succeed although it should fail
  5. Change vunit_hdl installation to 4.7.0
  6. Execute python3 run.py *arb_wrr* --> This will fail (correct behavior)
Lenguaje dominante
VHDL
Estrellas
850
Forks
305
Merge medio
2 d 10 h
PR fusionados (30 d)
7

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