MultiClockSpec chiselTest fails with recent Verilator version
Maintainers usually reply within 1 day
Assessment
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Newbie friendliness
- 68/100
- Issue type
- Bug
- Clarity
- Mostly clear
- Activity status
- Quiet
- Tech stack
- scala
- Domain
- testing-qa
Research direction
Run ./mill chisel[].test.testOnly chiselTests.MultiClockSpec with Verilator v5.046 and compare the failure at MultiClockSpec.scala:26 against a version that passes. Read the ClockDividerTest path and generated assertion context; done means the test passes with the affected simulator versions and the regression is covered by the relevant test or CI setup.
Written by the indexing model from the issue text.
Description
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Install Verilator >= v5.046, then run ./mill chisel[].test.testOnly chiselTests.MultiClockSpec
[40] %Error: ClockDividerTest_Verification_Assert.sv:72: Assertion failed in TOP.svsimTestbench.dut.verification_assert: Assertion failed at MultiClockSpec.scala:26
Problem not flagged by CI, because the Chisel CI pipeline uses a nightly build from verilator, provided by oss-cad-suite on 2023-06-21.
./verilator --version
Verilator 5.013 devel rev v5.012-12-g9ee5fd058
I confirmed that the testcase passes if using Verilator <= v5.044.
What is the expected behavior?
The ClockDividerTest should pass, independent of simulator version.
Please tell us about your environment:
Verilator v5.046 on linux-x64.
- Dominant language
- Scala
- Stars
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- Avg merge
- 1d 23h
- Merged PRs (30d)
- 9
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