Xilinx/finn

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Dataflow compiler for QNN inference on FPGAs

Stars: 1.1k
Forks: 308
Open beginner issues: 1
Indexed issues: 72
Avg merge: 3d 5h
Merged PRs (30d): 16

Dominant language: Python
License: BSD-3-Clause
Last GitHub push: Sep 6, 2026
Latest indexed: Sep 20, 2026
Contributing guide: Contributing guide
Code of conduct: No code of conduct
Beginner labels: good first issue

Beginner friendly Everything

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71 open issues indexed

Pool has no bit width minimization: accumulator/output widths derived at conversion time are never revisited Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 68/100

Xilinx/finn#1695 · Opened Sep 17, 2026
Pool (MaxPool): output datatype does not follow the input, `get_output_datatype` asserts `odt == idt` Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 52/100

Xilinx/finn#1694 · Opened Sep 17, 2026
Cyclic dependency between bit width minimization and layer specialization Open

bug

Difficulty 5/5 Over a week Newbie friendliness 30/100

Xilinx/finn#1693 · Opened Sep 17, 2026
mvu_4sx4u.sv: part-select p3[52:21] out of range [47:0] for ACCU_WIDTH>27 (SIMD=1/PE=2) breaks synthesis Open

Difficulty 3/5 1-2 days Newbie friendliness 72/100

Xilinx/finn#1681 · 1 comment · Opened Aug 31, 2026
ISSUE regarding mem_mode = external Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1549 · 2 comments · Opened Mar 26, 2026
LUT usage regression inside memstreamer/MVAU Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1513 · 1 comment · Opened Jan 28, 2026
Error during verification after step_qonnx_to_finn Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 30/100

Xilinx/finn#1484 · 11 comments · Opened Nov 16, 2025
Using approximate computing possiblity Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 20/100

Xilinx/finn#1453 · Opened Oct 13, 2025
Make timeout limit for fifo sim configurable Open

enhancement

Difficulty 2/5 1-3 hours Newbie friendliness 72/100

Xilinx/finn#1435 · 4 comments · Opened Sep 24, 2025
Why is there a hardcoded limit for the AXI-Lite Interfaces? Open

Difficulty 3/5 1-2 days Newbie friendliness 38/100

Xilinx/finn#1433 · Opened Sep 23, 2025
Force Pool layer to unfold further also if ConvInputGen doesn't meet target fps Open

enhancement

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1432 · Opened Sep 22, 2025
Check parallelism of ConvInputGen and related Pool Layer Open

enhancement

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1431 · Opened Sep 22, 2025
Check the prerequisite steps for the verification flow before executing Open

enhancement

Difficulty 4/5 3-5 days Newbie friendliness 55/100

Xilinx/finn#1428 · 1 comment · Opened Sep 22, 2025
Not getting the accuracy for Radioml_with_cnns on FPGA Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#1426 · 1 comment · Opened Sep 22, 2025
AssertionError with set_top <name> variable missing Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1417 · 6 comments · Opened Sep 1, 2025
AssertionError: cycle-free graph violated: partition depends on itself Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1399 · 3 comments · Opened Jul 27, 2025
tfc_end2end_example has pynq driver python dependency issues when trying to be deployed on FPGA Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1371 · 5 comments · Opened Jun 22, 2025
Exception: Synthesis failed, no bitfile found. Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1368 · 4 comments · Opened Jun 17, 2025
permission denied for creating mount space when trying to ./run-docker.sh quickstart Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 28/100

Xilinx/finn#1363 · 2 comments · Opened Jun 10, 2025
step syntheisze bitfile doesn't finish Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#1320 · 5 comments · Opened Apr 12, 2025
[VitisLink] Unsupported bitwidth 4096 when linking multiple StreamingDataflowPartitions together Open

bug

Difficulty 5/5 Over a week Newbie friendliness 25/100

Xilinx/finn#1276 · 2 comments · Opened Feb 11, 2025
MobileNetV1 - "size of variable 'srl' is too large to handle" from Q_srl.v at step "step_out_of_context_synthesis" Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 28/100

Xilinx/finn#1260 · 4 comments · Opened Jan 10, 2025
Issue with ResNet18 Context Synthesis Step 16/19 in FINN - Possible BRAM, CPU RAM or FPGA Size Limitation? Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#1256 · 5 comments · Opened Jan 7, 2025
Pynq ZU Support for TFC end2end example Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

Xilinx/finn#1228 · 3 comments · Opened Nov 13, 2024
Vitis HLS synthesis front-end OOM crash for some MVAU configs Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 32/100

Xilinx/finn#1214 · 2 reactions · Opened Oct 15, 2024
Data Mismatch in Default FINN FPGA Flow Tutorial Using MNIST Numerals Example Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#1211 · 1 comment · Opened Oct 10, 2024
Quicktest fail because of deprecated api call Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#1191 · 15 comments · Opened Sep 19, 2024
Getting error in step "step_set_fifo_depths" when running on FINN 0.9 Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#1178 · 5 comments · Opened Sep 6, 2024
IP definition not found for VLNV Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#1154 · 2 comments · Opened Aug 8, 2024
Adding typing annotations to FINN Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

Xilinx/finn#1146 · 1 comment · 2 reactions · Opened Aug 1, 2024
Drop in accuracy of Output between quantized Brevitas model and the streamlined Finn onnx model output. Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

Xilinx/finn#1088 · Opened May 24, 2024
Build and deploy DNNs on non-zynq ? Artix-7 Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 15/100

Xilinx/finn#1075 · Opened May 15, 2024
Strided pointwise convolution on rectangular feature maps not correctly handled by InferConvInpGen Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 45/100

Xilinx/finn#1033 · 4 comments · Opened Apr 8, 2024
OPSET and Assuming 4D input is NCHW Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#993 · 1 comment · Opened Feb 25, 2024
Clipping thresholds to input range + 1? Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#978 · 4 comments · Opened Feb 8, 2024
Cyclic-free graph violated error in TFC for BBN-PYNQ example for 2w2a (weight 2 bits, activation 2bits) Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#938 · 16 comments · Opened Dec 10, 2023
Error in parent_model = model.transform(CreateDataflowPartition() Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#936 · 8 comments · Opened Dec 10, 2023
Expand support for grouped convolutions Open

enhancement

Difficulty 5/5 Over a week Newbie friendliness 25/100

Xilinx/finn#918 · Opened Nov 9, 2023
Problematic transformations while streamlining of scaled dot-product attention Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#878 · 6 comments · 3 reactions · Opened Aug 28, 2023
There does not seem to be support for multi-way connection structures Open

bug

Difficulty 5/5 Over a week Newbie friendliness 20/100

Xilinx/finn#865 · 2 comments · Opened Jul 28, 2023
cycle-free graph violated: partition depends on itself Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#863 · Opened Jul 26, 2023
Im2Col_0: Dilation value != 1 is not supported for square convolutions Open

bug

Difficulty 5/5 Over a week Newbie friendliness 35/100

Xilinx/finn#860 · 6 comments · Opened Jul 20, 2023
Problems with inference in PYNQ-Z1 and emulation stitched IP Open

bug

Xilinx/finn#855 · 14 comments · 2 assignees · Opened Jul 15, 2023
AssertionError: Im2Col_0: ConvolutionInputGenerator1D works only for 1D convs Open

Difficulty 4/5 3-5 days Newbie friendliness 38/100

Xilinx/finn#814 · 2 comments · Opened May 10, 2023
Need Transpose Before Flatten Layer 1D model Training Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#807 · 2 comments · 1 reaction · Opened Apr 28, 2023
Obtained different result after calling an IP several times, seems like the data did not work properly inside. Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#796 · 12 comments · Opened Apr 8, 2023
Unable to run a container from maltanar/finn:dev_latest Open

Difficulty 3/5 1-2 days Newbie friendliness 25/100

Xilinx/finn#706 · 3 comments · Opened Oct 30, 2022
Signed output requres actval < 0 Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 35/100

Xilinx/finn#682 · 2 comments · 3 reactions · Opened Sep 16, 2022
Exception: Found multiple get_by_name matches, undefined behavior Open

bug

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/finn#681 · 2 comments · Opened Sep 16, 2022
Throughput and Latency reports from RTL sim Open

bug

Difficulty 3/5 1-2 days Newbie friendliness 45/100

Xilinx/finn#663 · 2 reactions · Opened Aug 10, 2022

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