Xilinx/XilinxVirtualCable

View on GitHub

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

Stars: 289
Forks: 97
Open beginner issues: 0
Indexed issues: 6

Dominant language: C
License: No license data
Last GitHub push: Jun 4, 2026
Latest indexed: Sep 21, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: No beginner labels indexed
PR merge metrics: No merged PRs in 30d

Beginner friendly Everything

Open All

6 open issues indexed

XVC server on Versal doesn't work Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

Xilinx/XilinxVirtualCable#26 · Opened Aug 5, 2026
very slow Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

Xilinx/XilinxVirtualCable#23 · Opened Mar 19, 2026
xvcService.c stack smashing detected Open

Difficulty 2/5 1-3 hours Newbie friendliness 48/100

Xilinx/XilinxVirtualCable#17 · Opened Jun 21, 2024
Support for U250 and U280 Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

Xilinx/XilinxVirtualCable#14 · 1 comment · Opened Nov 4, 2021
XVC Server causes freezes to linux when other user application is running Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

Xilinx/XilinxVirtualCable#7 · 10 comments · Opened Nov 6, 2019
About JTAG mux or bridge to enable multiple target FPGA connections Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

Xilinx/XilinxVirtualCable#3 · 3 comments · Opened Feb 5, 2018

Xilinx/XilinxVirtualCable

Get new issues in your inbox