flag_missing_ports false negative

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Assessment

Difficulty
4/5
Estimated time
3-5 days
Newbie friendliness
45/100
Issue type
Bug
Clarity
Mostly clear
Activity status
Quiet
Domain
testing-qa

Research direction

Start with the attached reproduction archive and run the provided klayout -b -r gf180mcu.lvs command using check_ports=true and top_lvl_pins=true. Compare the schematic’s separate SUB and W nets with the layout result to trace why flag_missing_ports reports an LVS pass; the issue does not name a source file or test. Done means this case reports the missing-port mismatch instead of passing.

Written by the indexing model from the issue text.

Description

Hi Matthias,

When implementing flag_missing_ports on gf180, I stumbled on a situation in which I got an LVS clean, but it should have failed.

I have a bad schematic file:

.SUBCKT ppolyf_u_nwell MINUS PLUS SUB

R1 MINUS $1 W ppolyf_u L=35.7U W=0.8U
R2 $1 $2 W ppolyf_u L=35.7U W=0.8U
R3 $2 $3 W ppolyf_u L=35.7U W=0.8U
R4 $3 $4 W ppolyf_u L=35.7U W=0.8U
R5 $4 $5 W ppolyf_u L=35.7U W=0.8U
R6 $5 $6 W ppolyf_u L=35.7U W=0.8U
R7 $6 $7 W ppolyf_u L=35.7U W=0.8U
R8 $7 PLUS W ppolyf_u L=23U W=0.8U

.ENDS

Notice that the SUB and W are separate nets. In layout however, they are the same net.
When I run the LVS with flag_missing_ports I get an incorrect LVS pass, even if it is quite clear from the window that something is wrong:

Image
How to reproduce

Download this file: flag_missing_ports_klayout.zip

unzip flag_missing_ports_klayout.zip
cd flag_missing_ports
klayout -b -r gf180mcu.lvs -rd input=ppolyf_u_nwell.gds.gz -rd schematic=ppolyf_u_nwell.cdl -rd report=ppolyf_u_nwell.lvsdb -rd check_ports=true -rd top_lvl_pins=true

I initially thought that this was because I was making simplifications on the schematic netlist, but even when manually deleting these from the gf180mcu.lvs script, the behavior is still the same.

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