flag_missing_ports flags all internal nets for source subcircuits with no ports
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Assessment
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Newbie friendliness
- 35/100
Research direction
Start by reading the flag_missing_ports implementation and its flag_missing_port helper, then run the IHP-Open-PDK regression command from the issue. Focus on the case where the source SPICE top cell has no ports. Done means that case no longer reports internal nets as ports or produces the resulting mismatch.
Written by the indexing model from the issue text.
Description
Requires at least klayout 0.30.2 (flag_missing_port helper routine).
@klayoutmatthias Thanks for the port check enhancement. That has helped find discrepancies in standard cell port labeling.
However, we noticed that when the source spice top cell has no ports, then all of the internal nets are considered ports and cause a mismatch.
You can verify this with the IHP-Open-PDK repo test cases.
git clone https://github.com/H-Ojiro/IHP-Open-PDK.git --depth=1 -b port_check
cd IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing
python3 run_regression.py RES
Here's the spice
.SUBCKT rppd
Rp1 net1 net2 rppd m=1 l=0.5u w=0.5u
Rp2 net3 net4 rppd m=1 l=1u w=0.5u
Rp3 net5 net6 rppd m=1 l=1.2u w=0.7u
Rp4 net7 net8 rppd m=1 l=1.5u w=0.5u ps=0.2u b=1
Rp5 net9 net10 rppd m=1 l=1.7u w=0.5u ps=0.2u b=2
...
The layout has no text.
CC: @H-Ojiro
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