GICv3 ESPI enable and routing use incorrect distributor registers
Maintainers usually reply within 1 day
@La1itchauhan is already working on this.
Since Oct 17, 2026.
Assessment
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Newbie friendliness
- 78/100
Research direction
Read val/driver/gic/v3/gic_v3_extended.c and the extended distributor register definitions. Check v3_enable_extended_interrupt_source() and v3_route_extended_interrupt() against the expected register names and offsets in the issue. Done when ESPI enabling uses GICD_ISENABLERE and routing starts at GICD_IROUTERnE with the INTID relative to EXTENDED_SPI_START_INTID.
Written by the indexing model from the issue text.
Description
Two issues were identified in val/driver/gic/v3/gic_v3_extended.c.
1. Incorrect register used to enable an ESPI
v3_enable_extended_interrupt_source() writes to GICD_ICENABLERE, which is the clear-enable register and therefore disables the interrupt.
Current code:
val_mmio_write(val_get_gicd_base() + GICD_ICENABLERE
+ (4 * regOffset), 1 << regShift);
Expected code:
val_mmio_write(val_get_gicd_base() + GICD_ISENABLERE
+ (4 * regOffset), 1 << regShift);
GICD_ISENABLERE should be defined as 0x1200 alongside the other extended distributor register definitions.
2. Incorrect address calculation for ESPI routing
v3_route_extended_interrupt() uses the standard SPI GICD_IROUTERn base and indexes it using the complete ESPI INTID.
Current code:
val_mmio_write64(gicd_base + GICD_IROUTERn
+ (int_id * 8), cpuTarget);
For ESPI INTID 4096, this accesses offset 0xE100, which is incorrect.
Extended SPI routing starts at GICD_IROUTERnE, offset 0x8000, with ESPI INTID 4096 corresponding to register zero.
Expected code:
val_mmio_write64(gicd_base + GICD_IROUTERnE
+ ((int_id - EXTENDED_SPI_START_INTID) * 8U),
cpuTarget);
The existing GICD_IROUTERnE definition can be reused.
- Dominant language
- C
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- Merged PRs (30d)
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