Synthesis of Duplicate Imports

I have a design where I have imported 2 projects that use common custom circuits. The design simulates and executes ok. When I synthesize the design, I get '"XXXXXX". This is not allowed, please make sure all sheets have a unique name'. The board is set to use Vivado (if that matters). Question - is this by design? If so, it limits the utility of reusable components...is there a workaround?

This seems like a limitation that could be avoided if the DRC looked to see if the circuits are identical (and/or imported) and only generated the one definition.