The-OpenROAD-Project/OpenROAD

Add some good examples from antonblanchard/vlsiffra as a regression test / benchmark

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#2,361 创建于 2022年10月12日

 (8 条评论) (0 个反应) (2 位负责人)Verilog (903 个派生)auto 404
Stalegood first issue

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描述

@antonblanchard just released the vlsiffra project. See the tweet @ https://twitter.com/antonblanchard/status/1580154261962657792 

Introducing https://github.com/antonblanchard/vlsiffra/ - a generator of fast and efficient standard cell adders, multipliers and multiply-adders. Written in Amaranth HDL, formally verified with #Yosys. #Verilator verification too With @OpenROAD_EDA + ASAP7 7nm a 32bit 3 cycle multiplier hits 2.7GHz

Some interesting aspects;

  • vlsiffra is written in the Amaranth HDL language which allows it to be very configurable, including
  • vlsiffra currently supports the SkyWater sky130hd, GlobalFoundries GF180MCU and ASAP7 PDKs and standard cell libraries.
  • vlsiffra only requires a few standard cells (full and half adders, 2 input xor, 2 input and, inverter as well as a couple of more complicated cells (ao21, ao22, ao33)

It seems like some of the output of this tool would make excellent OpenROAD regression tests / benchmarks.

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