looking for cooperate on verilog converter

Hi My name is Peter, system architect from www.quantr.foundation, we are team of 7 in Hong Kong working on RISC-V cpu. We have huge passion on low-level stuff. We want to create a verilog converter, to convert verilog into logisim and simulate it, mainly for education purpose. We have our own verilog parser built by antlr. We have used it to build our own verilog preprocessor https://www.quantr.foundation/project/?project=Verilog%20Compiler and debugger https://www.youtube.com/watch?v=cPjEUe2uY8I . That prove we are serious.

Now we want to find partners, especially on consulting roles.

1. We want to know how to translate verilog into ray logic, only compose by d-latch and gates.
2. We don't know how to import thing to logicism, need some guidance on hacking the logicsim

thanks Peter