[AArch64] Add SimplifyDemandedVectorEltsForTargetNode support for AArch64ISD::DUPLANE nodes · llvm/llvm-project#87497 | Good First Issue

(13 留言) (0 反應) (1 負責人)C++ (10,782 fork)batch import

backend:AArch64good first issue

倉庫指標

Star: (26,378 star)
PR 合併指標: (平均合併 1天 2小時) (30 天內合併 1,000 個 PR)

描述

Noticed on #86284 - aarch64 is missing SimplifyDemandedVectorElts handling to/from AArch64ISD::DUPLANE nodes

Extend performDUPCombine to call SimplifyDemandedVectorElts from AArch64ISD::DUPLANE nodes as we only demand that one lane element.
Add AArch64TargetLowering::SimplifyDemandedVectorEltsForTargetNode to handle AArch64ISD::DUPLANE nodes (and AArch64ISD::DUP?) - if we only demand the dup lane index we might be able to remove the node entirely.
The hadd-combine.ll tests might be enough, but we could require some additional test coverage.

貢獻者指南

研究方向: 檢查 AArch64ISelLowering.cpp 中現有的 performDUPCombine 函數，並理解其他目標如何實現 SimplifyDemandedVectorElts。然後逐步實現更改：首先擴展 performDUPCombine 以呼叫 SimplifyDemandedVectorElts，然後添加目標特定的回調，最後使用 hadd combine.ll 測試進行驗證。重點關注 DUPLANE 節點如何僅需求一個通道元素，以及如果只需求該通道時如何移除整個節點。
技術棧: cpp
領域: backend
議題類型: 功能
難度: 3
預計時間: 3-5 天
活動狀態: 活躍
清晰度: 清晰
前置要求: GitC++
新手友善度: 40