Does not stop on breakpoints.

Reproduce the F5 workflow with the Raspberry Pi Pico 2, the Debug Probe, and the launch.json settings for haltAfterReset. Compare behavior using the probe-rs list/info output, then inspect the main.rs breakpoint and impls.rs exception path. Done means breakpoints stop execution and RTT defmt messages remain available without requiring BOOTSEL mode.

My setup:

rpi4 + vs code + official extension, rpi pico 1w as debugprobe (v2.3.0/debugprobe_on_pico.uf2) , the target: rpi pico 2. Everything connected correctly via debug pins (swd).
I use "New Rust Project"
The option "Flash Project (SWD)" is inaccessible (greyed).
"Run Project (USB)" executes the program correctly but only when pico2 is in the BOOTSEL mode. However, in this case RTT defmt does not work.
Setting "haltAfterReset": true in launch.json and pressing F5 begins execution (after fleshing, even if not in the BOOTSEL mode) and pauses with "Exception has occured" message (no further info) on line 365 of impls.rs. After clicking F5 again the execution continues and RTT defmt messages are correctly displayed. However, execution does not stop on my breakpoints in main.rs .
Setting ""haltAfterReset": false" and pressing F5 executes the code, but does not display RTT defmt at all and also does not stop on breakpoints.

The above happens in v2.3.0 and also in v.2.2.3.

probe-rs list
The following debug probes were found:
[0]: Debugprobe on Pico (CMSIS-DAP) -- 2e8a:000c-0:E663682593294F35 (CMSIS-DAP)

probe-rs info
Probing target via JTAG

Error while probing target: The protocol 'JTAG' could not be selected.

Caused by:
    The probe does not support the JTAG protocol.
Probing target via SWD

ARM Chip with debug port Default:

Debug Port: DPv3, MINDP, Designer: ARM Ltd
├── 0x2000 Memory Access Port v2 (Coresight Component)
│   ├── 0xe00ff000 ROM Table (Class 1), Designer: ARM Ltd
│   ├── 0xe000e000 Processor debug architecture (ARMv8-M) (Coresight Component)
│   │   └── CPUID
│   │       ├── IMPLEMENTER: ARM Ltd
│   │       ├── VARIANT: 1
│   │       ├── PARTNO: Cortex-M33
│   │       └── REVISION: 0
│   ├── 0xe0001000 DWT architecture (Coresight Component)
│   ├── 0xe0002000 FPB architecture (Coresight Component)
│   ├── 0xe0000000 ITM architecture (Coresight Component)
│   ├── 0xe0041000 ETM architecture (Coresight Component)
│   └── 0xe0042000 CTI architecture (Coresight Component)
├── 0x4000 Memory Access Port v2 (Coresight Component)
│   ├── 0xe00ff000 ROM Table (Class 1), Designer: ARM Ltd
│   ├── 0xe000e000 Processor debug architecture (ARMv8-M) (Coresight Component)
│   │   └── CPUID
│   │       ├── IMPLEMENTER: ARM Ltd
│   │       ├── VARIANT: 1
│   │       ├── PARTNO: Cortex-M33
│   │       └── REVISION: 0
│   ├── 0xe0001000 DWT architecture (Coresight Component)
│   ├── 0xe0002000 FPB architecture (Coresight Component)
│   ├── 0xe0000000 ITM architecture (Coresight Component)
│   ├── 0xe0041000 ETM architecture (Coresight Component)
│   └── 0xe0042000 CTI architecture (Coresight Component)
├── 0x6000 SoC-600 Timestamp Generator (Core Link / Prime Cell / System component)
├── 0x7000 SoC-600 ATB Funnel (Coresight Component)
├── 0x8000 SoC-600 TPIU    (Coresight Component)
├── 0x9000 CTI architecture (Coresight Component)
└── 0x0000 RP235x CoreSight ROM (Coresight Component)