B-Lang-org/bsc
Generate appropriate empty argument lists for Verilog system tasks/functions
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#304 aberto em 3 de fev. de 2021
good first issuepre-github
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Description
When system tasks appear in the generated Verilog, this code in Verilog.hs omits the parenthesis when there are no arguments:
-- no parens when calling a task if it has no arguments
pPrint d p (VTask task []) = pPrint d 0 task <> text ";"
This was probably added because that is how the Verilog standard says that $finish should be written. However, for $fflush, the standard says that it must have empty parentheses, and some tools will be sticklers and issue a warning if the parentheses are missing.
The pPrint code will probably need to check the task name, to handle each specifically.
This is bug 1925 in Bluespec Inc's pre-GitHub bug database.