[test] Versions of Verilator >= 5.0 require --timing or --no-timing options for top level sim builds
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Assessment
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Newbie friendliness
- 72/100
- Issue type
- Bug
- Clarity
- Mostly clear
- Activity status
- Quiet
- Domain
- build-system, testing-qa
Research direction
Start with vio_pgd.sv and vcc_pgd.sv, then reproduce the failure through the getting started tests using Verilator 5 or newer. Check the simulator build's handling of the timing delays and verify that the affected top-level simulation builds successfully while remaining compatible with older Verilator versions.
Written by the indexing model from the issue text.
Description
Description
While running the getting started tests recently I found myself coming up against Verilator build issues - it turns out that from version 5 onwards verilator requires either a --timing or a --no-timing option to be passed when it finds timing delays in any files.
The vio_pgd.sv & vcc_pgd.sv files contain some delays so it won't build the sim.
There are a few options to fix but I think the only backwards compatible option is to wrap up the delays in /*verilator timing_off*/ & /*verilator timing_on*/ meta comments - I can put together a PR for this if there is interest in supporting higher versions of verilator?
- Dominant language
- SystemVerilog
- Stars
- 3.7k
- Forks
- 1.1k
- Avg merge
- 3d 1h
- Merged PRs (30d)
- 149
Contributor guide
First steps
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