`ethernet_csr.sv` needs refactoring

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Assessment

Difficulty
5/5
Estimated time
Over a week
Newbie friendliness
35/100
Issue type
Refactor
Clarity
Needs clarification
Activity status
Quiet

Research direction

Start by reading ethernet_csr.sv and identify how its registers relate to the RDL source. The issue does not name an automated generator, entry point, or tests, so determine the project’s intended register-generation flow before starting. Done means the CSR is generated through that flow and no longer risks going out of sync with the RDL.

Written by the indexing model from the issue text.

Description

ethernet_csr.sv works but is a little bit difficult to read. It would be best to migrate to an automated register generator flow to avoid going out of sync with RDL

Dominant language
SystemVerilog
Stars
23
Forks
12
PR merge metrics
No merged PRs in 30d

Contributor guide

No contributing guide indexed for this repository

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

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