defect [HDL]: HDL creation fails for Random generator component with 64bits

Hi Team,

the attached example shows the LE Random generator component with 64 data bits. As s_initSeed only uses 48 bits, the output process to write the output register shows the error below.

msg: Error (10393): VHDL error at LogisimRNG_behavior.vhd(121): left bound (63) of slice must belong to range (47 downto 0) of corresponding object Error (12152): Can't elaborate user hierarchy "main:CIRCUIT_0|LogisimRNG:MEMORY_1"

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main_behavior.vhd:

... MEMORY_1 : LogisimRNG GENERIC MAP ( nrOfBits => 64, seed => X"00000020" ) PORT MAP ( clear => s_logisimNet11, clock => logisimClockTree0(4), enable => s_logisimNet1, q => s_logisimBus0(63 DOWNTO 0), tick => logisimClockTree0(2) ); ...

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logisimRND_behavior.vhd: ...

SIGNAL s_initSeed : std_logic_vector( 47 DOWNTO 0 );

...

s_initSeed <= x"0005DEECE66D" WHEN seed = x"00000000" ELSE x"0000"&seed; ...

makeOutput : PROCESS(clock, s_reset, s_initSeed) IS BEGIN IF (rising_edge(clock)) THEN IF (s_reset = '1') THEN s_outputReg <= s_initSeed( (nrOfBits-1) DOWNTO 0 ); ELSIF (tick = '1' AND enable = '1') THEN s_outputReg <= s_currentSeed((nrOfBits+11) DOWNTO 12); END IF; END IF; END PROCESS makeOutput;

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rnd_fail.zip

Thanks for looking into this