[AMDGPU][GlobalISel] Missing opcodes/intrinsics rules in AMDGPURegBankLegalize

There are missing opcode/intrinsic rules in AMDGPURegBankLegalizeRules.cpp for legalizing register banks depending on whether the instruction is uniform or divergent. Below is a list of opcodes/intrinsics that are missing. Note that this list may not be complete or up to date, some may have pull requests in review or have already been landed.

G_AMDGPU_FLAT_LOAD_MONITOR Done G_AMDGPU_GLOBAL_LOAD_MONITOR Done G_AMDGPU_SPONENTRY G_ATOMICRMW_USUB_COND In-progress G_ATOMICRMW_USUB_SAT In-progress G_BITCAST G_FCONSTANT G_FMAXIMUMNUM Done G_FMINIMUMNUM Done G_FPTOSI_SAT (In-progress, assigned to @asadium) G_FPTOUI_SAT (In-progress, assigned to @asadium) G_INTRINSIC_FPTRUNC_ROUND In-progress amdgcn_cluster_load_async_to_lds_b128 Done amdgcn_cluster_load_async_to_lds_b32 Done amdgcn_cluster_load_async_to_lds_b64 Done amdgcn_cluster_load_async_to_lds_b8 Done amdgcn_cluster_load_b128 Done amdgcn_cluster_load_b32 Done amdgcn_cluster_load_b64 Done amdgcn_cvt_f16_bf8 (In-progress, by @slant14) amdgcn_cvt_f16_fp8 (In-progress, by @slant14) amdgcn_cvt_f32_bf8 Done amdgcn_cvt_f32_fp8 Done amdgcn_cvt_f32_fp8_e5m3 Done amdgcn_cvt_off_f32_i4 Done amdgcn_cvt_pk_bf8_f16 amdgcn_cvt_pk_bf8_f32 Done amdgcn_cvt_pk_f16_bf8 amdgcn_cvt_pk_f16_fp8 amdgcn_cvt_pk_f32_bf8 Done amdgcn_cvt_pk_f32_fp8 Done amdgcn_cvt_pk_fp8_f16 amdgcn_cvt_pk_fp8_f32 Done amdgcn_cvt_pk_fp8_f32_e5m3 Done amdgcn_cvt_scalef32_2xpk16_bf6_f32 amdgcn_cvt_scalef32_2xpk16_fp6_f32 amdgcn_cvt_scalef32_f16_bf8 amdgcn_cvt_scalef32_f16_fp8 amdgcn_cvt_scalef32_f32_bf8 amdgcn_cvt_scalef32_f32_fp8 amdgcn_cvt_scalef32_pk32_bf6_f16 amdgcn_cvt_scalef32_pk32_f16_bf6 amdgcn_cvt_scalef32_pk32_f16_fp6 amdgcn_cvt_scalef32_pk32_f32_bf6 amdgcn_cvt_scalef32_pk32_f32_fp6 amdgcn_cvt_scalef32_pk32_fp6_f16 amdgcn_cvt_scalef32_pk_bf8_f16 amdgcn_cvt_scalef32_pk_bf8_f32 amdgcn_cvt_scalef32_pk_f16_bf8 amdgcn_cvt_scalef32_pk_f16_fp4 amdgcn_cvt_scalef32_pk_f16_fp8 amdgcn_cvt_scalef32_pk_f32_bf8 amdgcn_cvt_scalef32_pk_f32_fp4 amdgcn_cvt_scalef32_pk_f32_fp8 amdgcn_cvt_scalef32_pk_fp4_f16 amdgcn_cvt_scalef32_pk_fp4_f32 amdgcn_cvt_scalef32_pk_fp8_f16 amdgcn_cvt_scalef32_pk_fp8_f32 amdgcn_cvt_scalef32_sr_bf8_f16 In-progress amdgcn_cvt_scalef32_sr_bf8_f32 In-progress amdgcn_cvt_scalef32_sr_fp8_f16 In-progress amdgcn_cvt_scalef32_sr_fp8_f32 In-progress amdgcn_cvt_scalef32_sr_pk32_bf6_bf16 Done amdgcn_cvt_scalef32_sr_pk32_bf6_f16 Done amdgcn_cvt_scalef32_sr_pk32_bf6_f32 Done amdgcn_cvt_scalef32_sr_pk32_fp6_f16 Done amdgcn_cvt_scalef32_sr_pk32_fp6_f32 Done amdgcn_cvt_scalef32_sr_pk_fp4_f16 In-progress amdgcn_cvt_scalef32_sr_pk_fp4_f32 In-progress amdgcn_cvt_sr_bf8_f16 amdgcn_cvt_sr_bf8_f32 Done amdgcn_cvt_sr_f16_f32 amdgcn_cvt_sr_fp8_f16 amdgcn_cvt_sr_fp8_f32 Done amdgcn_cvt_sr_fp8_f32_e5m3 Done amdgcn_cvt_sr_pk_f16_f32 amdgcn_ds_atomic_async_barrier_arrive_b64 Done amdgcn_ds_atomic_barrier_arrive_rtn_b64 Done amdgcn_flat_prefetch Done amdgcn_frexp_exp In-progress amdgcn_global_load_tr4_b64 Done amdgcn_global_load_tr6_b96 Done amdgcn_global_prefetch Done amdgcn_global_store_async_from_lds_b128 Done amdgcn_global_store_async_from_lds_b32 Done amdgcn_global_store_async_from_lds_b64 Done amdgcn_global_store_async_from_lds_b8 Done amdgcn_load_to_lds In-progress amdgcn_log Done amdgcn_permlane_bcast Done amdgcn_permlane_down Done amdgcn_permlane_idx_gen Done amdgcn_permlane_up Done amdgcn_permlane_xor Done amdgcn_raw_buffer_load_async_lds In-progress amdgcn_raw_ptr_buffer_load_async_lds In-progress amdgcn_rcp Done amdgcn_rsq Done amdgcn_rsq_clamp Done amdgcn_s_alloc_vgpr Done amdgcn_sat_pk4_i4_i8 Done amdgcn_sat_pk4_u4_u8 Done amdgcn_s_bitreplicate In-progress amdgcn_set_inactive In-progress amdgcn_set_inactive_chain_arg In-progress amdgcn_sqrt Done amdgcn_struct_buffer_load_async_lds amdgcn_struct_ptr_buffer_load_async_lds amdgcn_unreachable Done amdgcn_wave_shuffle In-progress