llvm/llvm-project

[MLIR][affine] Proper handling of vector load / stores in Affine dialect and transformations

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#115,989 opened on Nov 13, 2024

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good first issuemlir:affine

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Description

In the context of Issue-115849 , I see that affine transformation is producing invalid IR like below where vector is being stored to a memref of size 1x1xf32.

affine.vector_store %5, %alloc[0, 0] : memref<1x1xf32>, vector<64x64xf32>

%6 = affine.vector_load %alloc[0, 0] : memref<1x1xf32>, vector<64x512xf32>

I think validity of the affine transformations need to be enhanced by introducing good verifiers.

Contributor guide

Research direction
Examine the affine dialect verifiers and transformations to ensure vector load/store sizes match memref dimensions.
Tech stack
cpp
Domain
compilers
Issue type
Bug
DifficultyEstimated implementation difficulty for a new contributor, from 1 for very small changes to 5 for expert-level work.
3
Estimated timeA rough time range for an experienced contributor to investigate, implement, test, and prepare a pull request.
1-2 days
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Active
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Clear
Prerequisites
C++MLIR basics
Newbie friendlinessA 1-100 score estimating how approachable this issue is for first-time contributors.
40