Update downstream backported patches for TPM GPIO locking

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Assessment

Difficulty
4/5
Estimated time
3-5 days
Newbie friendliness
48/100
Issue type
Refactor
Clarity
Mostly clear
Activity status
Active
Tech stack
linux

Research direction

Start by comparing coreboot reviews 90885 and 95545 to understand the corrected GPIO offsets and locking method. Update the downstream forks and AlderLake patchtrain, then test against nv4xadl. Done includes updating tpm-gpio-fail and the documentation, with the TODO items completed.

Written by the indexing model from the issue text.

Description

help wanted security SMM upstream
Skylake+ and possibly other platforms (t480*)

From discussion on coreboot matrix thread

Turns out the PCH-H datasheets are just wrong and the pad_cfg_lock_offset value for GPIO community 0 was wrong. I fixed it to match edk2-platforms and the Linux pin-ctrl driver and locking seems to be working with my original patch, though with the SBI method instead of the PCR method: https://review.coreboot.org/c/coreboot/+/90885
I will push some patches later
Locking them in SMM as is done in the patch train of https://review.coreboot.org/c/coreboot/+/95545 does not appear to be working on Skylake even with the corrected offsets.

AlderLake

Also patchtrain for alderlake (nv4x_adl), would needs backporting https://review.coreboot.org/q/topic:%22tpm_gpio_pltrst_lock%22 to be applied downstream until next release of Dasahro+Heads

Referred from https://github.com/Dasharo/coreboot/pull/959#issuecomment-5717812006


TODO
Dominant language
Makefile
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Merged PRs (30d)
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