enhancementgood first issue
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Descrizione
Steps to repro:
bsc -verilog -o Top.v Top.bs
Expected result: output goes into Top.v
Expected result, slightly darker timeline: -o flag is rejected as incompatible with Verilog output, compile fails.
Actual result: -o flag silently ignored, output goes into mkTop.v (as that is the name of the module in Top.bs).