B-Lang-org/bsc
bsc does not update generated verilog/sim when BSV preprocessor macros changed
Aperta
#290 aperta il 8 gen 2021
good first issue
Metriche repository
- Star
- (1108 stelle)
- Metriche merge PR
- (Merge medio 17g 1h) (18 PR mergiate in 30 g)
Descrizione
package A;
module mkA();
`ifdef MY_MACRO
// behavior 1
rule behavior_1;
$display("behavior 1");
endrule
`else
// behavior 2
rule behavior_2;
$display("behavior 2");
endrule
`endif
endmodule
endpackage
If I first run
bsc -verilog -g mkA -D MY_MACRO A.bsv
the generated verilog is based on the code in "behavior 1" block. But then, if I subsequently run:
bsc -u -verilog -g mkA A.bsv
The module is not recompiled and the Verilog is still based on "behavior 1" block. I expect bsc to analyze the module again and re-generate the verilog based on "behavior 2".
I need to manually remove the .bo files and rerun bsc to get the expected behavior.