Create an IP Checker Utility

Description

Originally posted by @rovinski in https://github.com/The-OpenROAD-Project/OpenROAD/issues/4871#issuecomment-2026137319

Currently, it is very possible to import an IP block which is poorly designed and will cause downstream issues in OpenROAD, which becomes difficult to root-cause. A checker utility which checks against a list of common problems can go a long way in identifying problems early.

Suggested Solution

List of common problems to check (far from an exhaustive list):

• LEF
  • Macro dimensions are a multiple of the manufacturing grid
  • Pins are aligned to the manufacturing grid
  • Each signal pin must obey one of the following:
    • Minimum width, and each pin lies on the routing grid (with an offset is okay)
    • Greater than minimum size, has an access point on the routing grid, and connections from a default width wire OR an NDR rule does not cause a DRC violation.
    • Pins are wide enough such that regardless of offset, a connection from a default width wire (OR NDR rule) does not cause a DRC violation.
  • Power ring or grid straps are accessible (no obstructions in the way)
  • Signal pins are accessible (no obstructions in the way)
  • LEF file does not have an excessive number of polygons which will slow down OR
  • Ports have antenna info
  • LEFs in finfet processes have a fin grid property
  • Pins have geometries
• LIB
  • All quantities (rise, fall, delay, power, cap, etc.) are sane
    • No instantaneous transitions for reasonable input values
    • No excessively long transitions for reasonable input values
    • No excessively large capacitances
  • No missing properties
  • Characterization corner(s) match(es) the characterization corner(s) of the design
• LIB+LEF
  • Every LEF digital pin has lib timing info
  • LEF power pins defined match lib power pins
  • LEF and LIB area match

Additional Context

No response