logisim-evolution/logisim-evolution

Removing the "-93" switch when validating VHDL

Geschlossen

#2.098 geöffnet am 22.11.2024

 (2 Kommentare) (0 Reaktionen) (0 zugewiesene Personen)Java (505 Forks)batch import
enhancementhelp wanted

Repository-Metriken

Stars
 (3.695 Sterne)
PR-Merge-Metriken
 (Durchschn. Merge 3T 18h) (47 gemergte PRs in 30 T)

Beschreibung

I successfully simulated a VHDL design using the process(all) construct, but validation failed, which is a significant issue. The failure during validation causes the corresponding circuit to be error-marked, even though the simulation runs without problems. Since the -93 switch is not used in simulation with vcom, it would be better to remove this switch from the validation process as well.

Contributor Guide