logisim-evolution/logisim-evolution
Removing the "-93" switch when validating VHDL
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#2.098 geöffnet am 22.11.2024
enhancementhelp wanted
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Beschreibung
I successfully simulated a VHDL design using the process(all) construct, but validation failed, which is a significant issue. The failure during validation causes the corresponding circuit to be error-marked, even though the simulation runs without problems. Since the -93 switch is not used in simulation with vcom, it would be better to remove this switch from the validation process as well.